Abstract: A 16-State adaptive NPML detector is provided for a tape drive which addresses weaknesses of a conventional fixed, 8-state EPR4 detector. Rather than having a fixed target channel, the detector is programmable to allow a range of target channels and can support “classical” partial response channels such as PR4 or EPR4 by programming predictor or whitening filter coefficients. In one embodiment, two filter coefficients may be set via XREG inputs or dynamically determined through the use of an LMS algorithm allowing the detector to adapt the predictor coefficients as data is being read. Another embodiment provides a detector for an EPR4 target in which the whitening filter has one coefficient. Components of the detection system include the detector itself, an LMS engine, a coefficient engine and a noise predictive or whitening filter. Coefficients from the LMS engine may be loaded or stored dynamically based upon conditions in the tape drive.

Abstract: Methods, logic, apparatus and computer program product write data, comprising less than a full Data Set, to magnetic tape. Data is received from a host, a do-not-interleave command is issued and C1 and C2 ECC are computed. Codeword Quad (CQ) sets are then formed. At least one CQ set of the Data Set is written to a magnetic tape in a non-interleaved manner and a Data Set Information Table (DSIT) is written to the magnetic tape immediately following the at least one written CQ set. An address transformation may be used to cancel interleaving. Writing a CQ set may include writing a plurality of contiguous instances of the CQ set to the magnetic tape to maintain the effectiveness of ECC capability.

Abstract: Writing data to magnetic tape is performed by receiving data from a host, establishing sub data sets, computing C1 and C2 ECC, forming Codeword Quad sets, writing a beginning Data Set Separator to a magnetic tape, writing a plurality of contiguous instances of the CQ Set to the magnetic tape and writing a closing DSS. The number of instances of each Codeword Pair is increased, thereby allowing the benefits of writing short tape records and improving reading reliability while reducing susceptibility to mis-tracking errors and large defects, and while reducing the negative impact on data reliability. Otherwise unused latency times are utilizing and therefore no performance penalty is incurred.

Abstract: Conventional C2 coding and interleaving for multi-track data tape in LTO-¾ do not support recording data onto a number of concurrent tracks which is not a power of two. Higher-rate longer C2 codes, which do not degrade error rate performance, are provided. An adjustable format and interleaving scheme accommodates future tape drives in which the number of concurrent tracks is not necessarily a power of two. A data set is segmented into a plurality of unencoded subdata sets and parity bytes are generated for each row and column. The parameters of the C2 code include N2 as the least common multiple of the number of possible tracks to which codeword objects are to be written. COs are formed from N2 C1 codewords, mapped onto a logical data track according to information within headers of the CO and modulation encoded into synchronized COs which are written to the tape.

Abstract: During a read-after-write operation on magnetic tape, a first SCO is formed which includes two encoded processed user data units and is one of T SCOs in a first SCO set. The user data units are each one of T user data units in first and second user data unit sets, respectively, within the first SCO set. The first SCO set is written to the magnetic tape and is immediately read. When an error is detected in one of the user data units, a second SCO is formed to include the first user data unit and, only if an error is not detected in a user data unit in the other user data unit set, to not include the other user data unit, the second SCO being one of T SCOs in a second SCO set. Then, the second SCO set is rewritten to a later position on the tape later.

Abstract: An encryption communications appliance provides data encryption management for a data storage library. The appliance is coupled to an encryption-capable storage device, a data storage library controller within the data storage library and with an encryption key manager (EKM). The encryption command communications appliance intercepts encryption key requests from the data storage device and transparently forwards the requests to the EKM. The appliance also forwards transparently communications between the library controller and the data storage device.

Abstract: For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1?K1 C1-parity bytes are generated for each row and N2?K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.

Abstract: Methods are provided for managing data encryption for a data storage library. An implementation assessment is performed for a customer and, in response to the implementation assessment, a set of customizations are generated for an encryption command communications appliance to enable the appliance to communicate with an encryption-capable storage device and a data storage library controller within the data storage library and with an encryption key manager (EKM) coupled to the data storage library. The encryption command communications appliance is configured with the set of customizations and the configured encryption command communications appliance is installed in the data storage library coupled to the library controller, the storage device and the EKM.

Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.

Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.

Abstract: An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of internal operations data. The BUIQ includes a unified issue queue UIQ 0 and a unified issue queue UIQ 1. The BUIQ may manage a particular VSU store instruction from one UIQ to determine data dependencies and employ the other UIQ to determine address dependencies of that particular VSU store instruction. The UIQs employ a dependency matrix including a dependency array. The dependency array data maintains both data and address dependency information. The particular VSU store instruction issues to execution units such as VSUs for data dependency information and load store units (LSUs) for address dependency information. A particular VSU store instruction may execute to provide data dependency information independent of address dependency information.

Abstract: An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

Abstract: Graphical User Interface (GUI) automation tools continue to evolve in their sophistication and complexity. However, it is still necessary to tailor such automation to the machine configuration that the test is being run on. This can be a costly and time consuming exercise when developing software for a myriad of different platforms. Broadly contemplated herein, in accordance with at least one embodiment of the invention, are arrangements and processes for recording a test solely on one machine while generating images on all the other available environments.

Abstract: In the context of middleware products, an arrangement wherein a sender tags messages with authorization information identifying those users or groups who are authorized to view or receive the messages. Thus, even if multiple users will be connected to the same queue for reading messages, only specific receivers/consumers will be able to get the messages. Not only is a comfortable degree of security ensured, but the need to waste system resources, e.g., by using multiple queues for different kinds of messages, is summarily avoided.

Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.

Abstract: A system and method are provided for enabling a user to search for documents that the user has previously viewed on its local machine. The system includes three main components: the desktop integration module, the index module, and the graphical user interface module. The desktop integration module is an application which monitors documents with which the user interacts for predetermined events, and obtains content data and metadata from the monitored documents. The index module indexes the content data and metadata received from the desktop integration module. The graphical user interface module then permits a user to utilize the desktop integration module and index module by allowing a user to search for a document.

Abstract: Systems and methods are provided for cooling an electronics rack and a computer room from a single unit, which includes a heat-generating electronics subsystem across which air flows from an air inlet to an air outlet side of the rack. First and second modular cooling units (MCUs) are associated with the rack and configured to provide system coolant to the electronics subsystem for cooling thereof. System coolant supply and return manifolds are in fluid communication with the MCUs for facilitating providing of system coolant to the electronics subsystem, and to an air-to-liquid heat exchanger associated with the rack for exclusively cooling air passing through the rack, as well as conditioning the ambient air of the computer room. Such cooling is exclusive of an outside-of-rack conditioned air unit.

Abstract: A knowledge model of CAD knowledge may be created using a modeling language such as SysML to improve maintainability and re-usability of knowledge, thereby reducing workload. The SysML knowledge model may be stored in a knowledge repository coupled to a knowledge server. The SysML knowledge model may be accessed through the knowledge server. The SysML knowledge model may be associated with elements of a CAD model, and one or more elements of the CAD model may be linked to one or more corresponding elements in the knowledge model. Thus, when a value of one or more elements is changed in the knowledge model, the results of the change are updated substantially immediately in both the CAD model and the knowledge model and other applications using the knowledge model.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A method for secure printing comprising receiving a user print request to print information from a computer terminal, wherein the computer terminal is located in a network and is assigned an internet protocol address, prompting the user for approval to instruct a designated printer to commence printing the print request, wherein the designated printer is connected to a network and is assigned an internet protocol address, determining whether the computer terminal and the designated printer are in the same network by comparing the first portion of the computer terminal's internet protocol address with the first portion of the designated printer's internet protocol address, and instructing the designated printer to commence printing if the computer terminal and the designated printer are determined to be in the same network.