Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module comprises two synchronous servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted parameter estimate and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. An offset computation module provides first and second offset terms which are summed with the unweighted parameter estimates. Multiplying nodes receive the unweighted parameter estimates and the weight signals and outputs offset weighted parameter estimates. A summing node receives the offset weighted parameter estimates and outputs a combined offset weighted parameter estimate to a servomechanism.

Abstract: A system and method are provided for enabling a user to search for documents that the user has previously viewed on its local machine. The system includes three main components: the desktop integration module, the index module, and the graphical user interface module. The desktop integration module is an application which monitors documents with which the user interacts for predetermined events, and obtains content data and metadata from the monitored documents. The index module indexes the content data and metadata received from the desktop integration module. The graphical user interface module then permits a user to utilize the desktop integration module and index module by allowing a user to search for a document.

Abstract: An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected.

Abstract: The present invention relates to a method for processing data entities by a data processing system, wherein: a first and a second set of data entities are stored in a main memory and associated with a respective first and second set of points of a domain; the first set of data entities is loaded into a local storage; one or more first calculations are performed using the first set of data entities to generate first calculated data; the second set of data entities is determined according to at least some of the first calculated data; the determined second set of data entities is loaded into the local storage; and one or more second calculations are performed using the second set of data entities resulting in second calculated data.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A method for transforming Extensible Markup Language (XML) data to Resource Description Framework (RDF) data. The method includes the steps of: receiving a predefined mapping file; retrieving the correspondences between XML elements and/or attributes in the XML data and/or properties and concepts of the RDF data as specified by the mapping file, wherein the correspondence is represented by elements of the mapping file; processing elements of the mapping file to obtain XML elements and/or attributes and generate corresponding RDF resources; and generating the RDF data by using the generated RDF resources. A corresponding transformation engine apparatus is configured to perform the foregoing method.

Abstract: A method of holding information for identifying a cause for an object becoming problematic and presenting the information to a user. The method ascertains the cause of memory consumption by a program in a computer system. This method includes: acquiring a first call path related to the creation of an object from a memory; acquiring a second call path related to the connection to the object from the memory; and determining a common part of the acquired first and second call paths, wherein the common part indicates the cause in the program.

Abstract: A virtual tape server (VTS) and a method for managing shared first level storage, such as a disk cache, among multiple virtual tape servers are provided. Such a system and method manage first level storage to accommodate two or more host processing systems by maintaining adequate free space in the cache for each host and by preventing one host, such as a mainframe, from taking over free space from another host, such as a Linux system.

Abstract: A method, system, and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, Ta, wherein the Ta is based on a dew point temperature, Tdp of a computer room. A second set point temperature, Tb, is measured, wherein the Tb is based on a facility chilled liquid inlet temperature, Tci, and a rack power, Prack, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, Tsp, is selected. The Tsp is the higher value of said Ta and said Tb. Responsive to the selected Tsp, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: A RAID system is provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A system that automatically prompts a computer user about a known limitation of a product component, such as a software component. Generally, there is contemplated herein a method including providing a physical computing device, running software in the physical computing device, detecting whether the software has a known limitation, and automatically providing an advisory responsive to detecting a known software limitation.

Abstract: In software development, the provision of a testing tool which includes a method for defining a data source dynamically during an execution run, instead of programming such a definition within test script.

Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module comprises two synchronous servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted parameter estimate and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. An offset computation module provides first and second offset terms which are summed with the unweighted parameter estimates. Multiplying nodes receive the unweighted parameter estimates and the weight signals and outputs offset weighted parameter estimates. A summing node receives the offset weighted parameter estimates and outputs a combined offset weighted parameter estimate to a servomechanism.

Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module servo module comprises two servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted metric and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. A first multiplying node receives a first unweighted metric and a first weight signal and is operable to output a first weighted metric. A second multiplying node receives a second unweighted metric and a second weight signal and outputs a second weighted metric. A summing node receives the first and second weighted metrics and outputs a combined weighted metric to an LPOS word decoder.

Abstract: A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate.