Abstract: The invention concerns an electronic circuit comprising a sigma-delta modulator and a power amplifier connected downstream thereof, wherein there is provided a feedback circuit (207) which is coupled between an output of the sigma-delta modulator and an input of the sigma-delta modulator and which includes an emulation of the signal path between the output of the sigma-delta modulator and the output of a power amplifier (107) connected downstream of said sigma-delta modulator.

Abstract: A CORDIC unit for the iterative approximation of a vector rotation through a rotary angle ? by a number of elementary rotations through elementary angles ?i, including elementary rotation stages for respectively affecting an elementary rotation through an elementary angle ?i as an iteration step in the iterative approximation. After such an elementary rotation there remains a residual angle through which rotation is still to be affected. The elementary rotation stages of the CORDIC unit are adapted for rotation through elementary angles ?i given by powers of two with a negative integral exponent. The CORDIC unit can also include a triggering device for triggering the elementary rotations, a triggering device which is adapted prior to each iteration step to compare the residual angle to at least one of the elementary angles and to omit those elementary rotation stages whose elementary angles are greater than the residual angle.

Abstract: The IEEE 802.11a standard uses OFDM, where the transmission is divided into several orthogonal sub-carriers. Here, an algorithm is used for the frame detection; a simplified differentiator obtains an absolute maximum in the differentiated signal at that point where the first plateau in JF(k) starts; a peak detector obtains the position of the absolute maximum in the differentiated signal, divides the problem into relative peak detection and falling edge detection; a simplified XNOR-based crosscorrelator is used, where the simplifications are based on the knowledge of the reference; a particular solution is provided for the CORDIC algorithm in the vectoring mode for arctangent calculation; hardware structuring is presented for the whole synchronizer so as to obtain a simple control mechanism and the separation of this structure into different clock domains, each one being activated only to perform its operation and deactivated afterwards.

Abstract: The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal in the form of a sequence of a plurality of digital partial signals associated with a number of subcarriers (k) of a carrier, the method including, for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. One embodiment provides the equalization with elimination of an accumulation of a phase error over the sequence of the partial signals. In addition the estimation includes detecting a plurality of predetermined pilot signals and determining a phase correction factor on the basis of the detected pilot signals, with at least one multiplication operation carried out solely by means of shift and adding operations. A corresponding apparatus is also described.

Abstract: The invention concerns a semiconductor component and an associated production process having a silicon-bearing layer, a praseodymium oxide layer and a mixed oxide layer arranged between the silicon-bearing layer and the praseodymium oxide layer and containing silicon, praseodymium and oxygen. It is possible because of the mixed oxide layer on the one hand to improve the capacitance of the component and on the other hand to achieve a high level of charge carrier mobility without the necessity for a silicon oxide intermediate layer.

Abstract: The invention concerns an asynchronous wrapper for a globally asynchronous, locally synchronous circuit. The asynchronous wrapper operates with a request signal-driven clock control, supplemented by a local clock unit in the absence of request signals. It has at least one input unit which is adapted to receive a request signal from outside and to indicate to the outside the reception of the request signal by the delivery of an associated acknowledgement signal, and a pausable clock unit which is adapted to repeatedly produce a first clock signal and to deliver it to an internally synchronous circuit block associated with the asynchronous wrapper. The input unit is adapted to produce, if a request signal is applied, a second clock signal which is in a defined time relationship with the request signal and to deliver it to the internally synchronous circuit block.

Abstract: The semiconductor device according to the invention includes a substrate, a field insulating region which delimits an active region of the semiconductor substrate, a collector, at least one collector contact region associated with the collector, and a base with an associated base connection region. The collector and the collector contact region are formed in the same active region. In addition the base connection region extends partially over the active region and is separated from the surface of the active region by an insulator layer.

Abstract: The invention concerns a bipolar transistor with an epitaxially grown base and a self-positioned emitter, whereby the base is formed from a first substantially monocrystalline epitaxial region (1) which is arranged in parallel relationship to the surface of the semiconductor substrate (2) and a second substantially polycrystalline and highly doped region (3) of the same conductivity type which is arranged in perpendicular relationship to the substrate surface and encloses the first region at all sides and that said second region, at least at one side but preferably at all four sides, is conductingly connected to a third, preferably highly doped or metallically conducting, high temperature-resistant polycrystalline layer (4) which is arranged in parallel relationship to the surface of the semiconductor substrate and forms or includes the outer base contact to a metallic conductor track system.

Abstract: A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the low doped drain region LDDR (22, 26) of the transistor is a doping zone (24) which is shallow in comparison with the penetration depth of the source/drain region (3, 5), of inverted conductivity type to the LDDR (22, 26) (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR (22, 26) and does not exceed a nett doping of 8E12 At/cm2.

Abstract: A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.

Abstract: The invention relates to a method for producing high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip. In order to produce these high-speed vertical npn bipolar transistors and complementary MOS transistors on a chip, all technological method steps for producing the vertical structure of the collector, base and emitter in the active region of the npn bipolar transistors as well as for laterally structuring the collector regions, base regions and emitter regions are performed before the troughs and the gate insulating layer for the MOS transistors are produced.

Abstract: The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxide is deposited onto a prepared wafer (12). A silicon layer (16) and on top of said silicon layer a cover layer (18) is deposited onto the metal oxide layer (14), said cover layer being laterally structured. In a subsequent tempering step in an oxygen-free, reducing gas atmosphere the silicon layer (16) and the metal oxide layer (14) are converted to a metal silicide layer in lateral sections (20, 22) in which the cover layer (18) was previously removed.

Abstract: An electronic component is disclosed having a first layer of metallically conductive material, a second layer of semiconductor material, and a third layer between the first and second layers. The third layer comprises a dielectric and at least inhibits charge carrier transport both from the first to the second layer and also from the second to the first layer. The dielectric comprises praseodymium oxide of the form Pr2O3 in predominantly single crystal phase, and the second layer comprises silicon with a (001)- or with a (111)-crystal orientation at an interface with the third-layer.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal which is present in a digital frequency representation in the form of a sequence of a plurality of digital partial signals which are associated with a number of subcarriers (k) of a carrier. The following steps are performed for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. An embodiment of that method provides that the equalization step includes the elimination of an accumulation of a phase error of the partial signal, caused by a sampling frequency error, over the sequence of the partial signals, such that the accumulation is negligible.

Abstract: In accordance with the invention the semiconductor capacitor includes a first capacitor electrode 1, a second capacitor electrode 3 and a capacitor dielectric 5 which is arranged between the two capacitor electrodes and which includes praseodymium oxide. It is distinguished in that the second capacitor electrode 3 includes praseodymium silicide.

Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.

Abstract: A CMOS-compatible DMOS transistor can be designed by virtue of a suitable layout configuration optionally for very high drain voltages or for power amplification at very high frequencies and which can be produced at a low level of additional cost in comparison with a conventional sub-?m production technology for CMOS circuits. A gate insulator of the transistor is of a unitary thickness under a control gate in the entire (active) region through which current flows. A zone of increased doping concentration (well region) which is near the surface and which determines the transistor threshold voltage is so arranged under the control gate that it occupies the entire area under the control gate which is on the active region and ends within a so-called drift space between the control gate and a highly doped drain region. The entire surface of the drift space is covered by a zone of the conductivity type of the drain region (VLDD), which is lowly doped in comparison with the highly doped drain region.

Abstract: A voltage-controlled oscillator device with an LC-resonant circuit, in particular for implementing integrated voltage-controlled oscillators for the lower GHz range, is disclosed. The device achieves continuous frequency tunability in a wide range in particular with a low level of phase noise and phase jitter. In the voltage-controlled oscillator, a second inductor can be periodically switched in parallel and/or in series with at least one first inductor of the LC-resonant circuit by way of a switching means actuated with the oscillator frequency. A control input of the switching means is connected to a variable dc voltage. In that respect the relationship of the duration of the conducting state and the duration of the non-conducting state of the switching means is variable within an oscillation period of the oscillator in dependence on the value of the control voltage.