Abstract: A sensor device including a deflectable membrane made of a 2D nanomaterial, a first optical waveguide for guiding light, disposed adjacent to the membrane and extending along the surface of the membrane at least in a first section, as well as a measuring device for measuring, within the first section the influence of the membrane on an evanescent wave range of the light guided along the first optical waveguide. The influence of the membrane on the light guided in the optical waveguide, in particular on the evanescent wave range of the light, can be measured interferometrically by detecting phasing differences or phase shifts. This allows for a force-free readout of the membrane deflection. By using very thin 2D nanomaterials, the membrane can also react to very quick changes in force.

Abstract: A sensor device including a deflectable membrane made of a 2D nanomaterial, a first optical waveguide for guiding light, disposed adjacent to the membrane and extending along the surface of the membrane at least in a first section, as well as a measuring device for measuring, within the first section the influence of the membrane on an evanescent wave range of the light guided along the first optical waveguide. The influence of the membrane on the light guided in the optical waveguide, in particular on the evanescent wave range of the light, can be measured interferometrically by detecting phasing differences or phase shifts. This allows for a force-free readout of the membrane deflection. By using very thin 2D nanomaterials, the membrane can also react to very quick changes in force.

Abstract: A chip antenna comprising at least one emitter which extends parallel to a main surface of a semiconductor substrate supporting the chip antenna, wherein the emitter is arranged on an island-like support zone of the semiconductor substrate, the support zone being surrounded by at least one trench which is completely filled with a gas, the trench passing through the entire depth of the semiconductor substrate and being bridged by at least one retaining web which forms a supporting connection between the support zone and the rest of the semiconductor substrate.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A hot hole transistor with a graphene base comprises on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer.

Abstract: The invention concerns an ultra-wideband information transmission method comprising a first encoding step on the part of the transmitter, in which a pulse group which is formed from a predetermined number of individual pulses is encoded in dependence on values of a random number sequence, and a correlation step on the part of the receiver in which correlation of a reception signal with a signal pattern is effected, wherein the signal pattern corresponds to the whole pulse group to be expected when using the same values of the random number sequence.

Abstract: A light emitting semiconductor device according the invention includes an SOI substrate, a collector and an injector. The SOI substrate includes a carrier layer, a buried oxide layer on the carrier layer, and a doped silicon layer structure with a conductivity type. The doped silicon layer structure with the conductivity type includes at least two silicon- or silicon germanium layers arranged adjacent to one another, wherein a dislocation network is configured in their interface portions at which dislocation network a radiative charge carrier combination with a light energy is provided, which light energy is smaller than a band gap energy of the silicon- or silicon germanium layers. The collector is formed as a pn-junction in a portion between the dislocation network and a surface of the silicon layer structure that is oriented away from the carrier layer, and wherein the injector is configured as a metal insulator semiconductor diode.

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.

Abstract: The present invention relates to a device (2000) and a method for encoding an input signal (102) into a digital pulse-width and/or phase modulated output signal (162). The present invention also relates to a transmission method, a power amplifier and a transmitter. With the aid of a mapping process comprising at least three-stages, a sequence of output pulses (162) is generated which corresponds on average over time to a theoretical, previously computed target pulse. In this way, the device (2000) or the method can be digitally implemented and a large part (100, 110) of the device (2000) can also be operated at a clock rate that is substantially lower than a clock rate of the output signal generator (200, 220).

Abstract: The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is associated with reduced susceptibility to circuit errors and a significantly reduced spatial requirement. The invention also relates to a method for checking the execution of the handshake protocol.

Abstract: A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed.

Abstract: A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.

Abstract: The invention relates to a microelectromechanical system with an electromechanical microswitch for switching an electrical signal in particular a radio frequency signal, in particular in a GHz range, comprising a multi-level conductive path layer stack arranged on a substrate, wherein conductive paths of the multi-level conductive path layer stack arranged in different conductive levels are insulated from one another through electrically insulating layers and electrically connected with one another through via contacts, an electromechanical switch which is integrated in a recess of the multi-level conductive path layer stack and which includes a contact pivot, an opposite contact and at least one drive electrode for the contact pivot, wherein the contact pivot, the opposite contact and the at least one drive electrode respectively form a portion of a conductive level of the multi-level layer stack.

Abstract: A thermoelectric semiconductor component, comprising an electrically insulating substrate surface and a plurality of spaced-apart, alternating p-type (4) and n-type semiconductor structural elements (5) which are disposed on said surface and which are connected to each other in series in an electrically conductive manner alternatingly at two opposite ends of the respective semiconductor structural elements by conductive structures, in such a way that a temperature difference (2?T) between the opposite ends produces an electrical voltage between the conductive structures or that a voltage difference between the conductive structures (7, 9; 13, 15) produces a temperature difference (2?T) between the opposite ends, characterized in that the semiconductor structural elements have a first boundary surface between a first and a second silicon layer, the lattice structures of which are considered ideal and are rotated by an angle of rotation relative to each other about a first axis perpendicular to the substrate su

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: The present invention relates to a device (2000) and a method for encoding an input signal (102) into a digital pulse-width and/or phase modulated output signal (162). The present invention also relates to a transmission method, a power amplifier and a transmitter. With the aid of a mapping process comprising at least three-stages, a sequence of output pulses (162) is generated which corresponds on average over time to a theoretical, previously computed target pulse. In this way, the device (2000) or the method can be digitally implemented and a large part (100, 110) of the device (2000) can also be operated at a clock rate that is substantially lower than a clock rate of the output signal generator (200, 220).

Abstract: A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.

Abstract: A light-emitting semiconductor component comprising a substrate which has a first interface between a first and a second silicon layer, whose lattice structures which are considered as ideal are rotated relative to each other through a twist angle about a first axis perpendicular to the substrate surface and are tilted through a tilt angle about a second axis parallel to the substrate surface, in such a way that a dislocation network is present in the region of the interface, wherein the twist angle and the tilt angle are so selected that an electroluminescence spectrum of the semiconductor component has an absolute maximum of the emitted light intensity at either 1.3 micrometers light wavelength or 1.55 micrometers light wavelength.

Abstract: An MEMS component including a monolithically integrated electronic component with a multi-plane conductor track layer stack which is arranged on a substrate and into which is integrated a cantilevered elastically movable metallic actuator which is arranged in the multi-plane conductor track layer stack at the level of a conductor track plane and is connected by via contacts to conductor track planes which are arranged thereabove or therebeneath and which apart from an opening in the region of the actuator are separated from the conductor track plane of the actuator by a respective intermediate plane insulator layer, wherein the actuator is formed from a metallically conductive layer or layer combination which is resistant to corrosive liquids or gases and which contains titanium nitride or consists of titanium nitride.

Abstract: A chip arrangement comprising a first chip having at least one first signal interface with first coupling elements arranged along a first line in a first number density and at least one second chip with at least one second signal interface with second coupling elements arranged along a second line in a second number density, where the first and second coupling elements permit contactless signal transmission between the first and second signal interfaces, where the two chips are so arranged relative to each other that coupling elements of the first and second signal interfaces can contactlessly transmit signals with each other, where the longitudinal extent of at least one of the signal interfaces along the line associated therewith is greater than the length of the overlap of the two longitudinal extents, and where one of the signal interfaces has a greater number density of coupling elements than the other.