Abstract: The present invention relates to a device (2000) and a method for encoding an input signal (102) into a digital pulse-width and/or phase modulated output signal (162). The present invention also relates to a transmission method, a power amplifier and a transmitter. With the aid of a mapping process comprising at least three-stages, a sequence of output pulses (162) is generated which corresponds on average over time to a theoretical, previously computed target pulse. In this way, the device (2000) or the method can be digitally implemented and a large part (100, 110) of the device (2000) can also be operated at a clock rate that is substantially lower than a clock rate of the output signal generator (200, 220).

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.

Abstract: The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is associated with reduced susceptibility to circuit errors and a significantly reduced spatial requirement. The invention also relates to a method for checking the execution of the handshake protocol.

Abstract: A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.

Abstract: The invention relates to a microelectromechanical system with an electromechanical microswitch for switching an electrical signal in particular a radio frequency signal, in particular in a GHz range, comprising a multi-level conductive path layer stack arranged on a substrate, wherein conductive paths of the multi-level conductive path layer stack arranged in different conductive levels are insulated from one another through electrically insulating layers and electrically connected with one another through via contacts, an electromechanical switch which is integrated in a recess of the multi-level conductive path layer stack and which includes a contact pivot, an opposite contact and at least one drive electrode for the contact pivot, wherein the contact pivot, the opposite contact and the at least one drive electrode respectively form a portion of a conductive level of the multi-level layer stack.

Abstract: The IEEE 802.11a standard uses OFDM, where the transmission is divided into several orthogonal sub-carriers. Here, an algorithm is used for the frame detection; a simplified differentiator obtains an absolute maximum in the differentiated signal at that point where the first plateau in JF(k) starts; a peak detector obtains the position of the absolute maximum in the differentiated signal, divides the problem into relative peak detection and falling edge detection; a simplified XNOR-based crosscorrelator is used, where the simplifications are based on the knowledge of the reference; a particular solution is provided for the CORDIC algorithm in the vectoring mode for arctangent calculation; hardware structuring is presented for the whole synchronizer so as to obtain a simple control mechanism and the separation of this structure into different clock domains, each one being activated only to perform its operation and deactivated afterwards.