Abstract: A switchable combiner and/or splitter circuit comprising at least two Wilkinson elements is suggested. The switchable circuit comprises one first terminal and for each Wilkinson element one pair of second terminals associated with the corresponding Wilkinson element. Each Wilkinson element connects the first terminal with the associated pair of second terminals. Each Wilkinson element includes a switchable component enabling selectively activating the associated pair of second terminals. The proposed solution combines a Single-Pole-Double-Through switch and a Wilkinson element and, thus, reduces the chip area required for integrating the circuit.

Abstract: An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal is suggested. The apparatus comprises a phase detector, a low-pass filter, a voltage-controlled oscillator, and a feedback loop forming a CDR loop. The voltage-controlled oscillator outputs a clock signal that is provided to the phase detector. The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit configured to receive the input signal and to generate two output signals having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate configured to receive the output signals from the interleave circuit and to generate an enable signal for the phase detector indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter converting the output signals from the interleave circuit into an MSB and an LSB bit stream.

Abstract: A lens for terahertz radiation, which can be used in an antenna arrangement, comprises a cylindrical lens body made of silicon having a planar front surface and a planar back surface. The lens body has a front body region which forms a silicon metamaterial with a relative permittivity that decreases in a lateral direction with increasing radial distance from a cylinder axis. A back body region is immediately adjacent to the front body region and extends to the back surface. It consists of bulk silicon having a laterally constant relative permittivity. The front body region comprises holes that are distributed on the front surface in rings that are concentric with respect to the cylinder axis. The holes extend from the front surface to respective hole bottoms at an equal bottom level in a depth direction. The hole bottoms interface with the back body region.

Abstract: The present invention relates to producing an electro-optical phase shifter such that it may be integrated into a front-end of line of an electronic-photonic integrated circuit. A conducting bottom layer with a first refractive index is provided. A center layer including a ferroelectric material and with a second refractive index is provided on top of a first region of the conducting bottom layer, such that the center layer is not on top of a second region of the conducting bottom layer. A conducting top layer with a third refractive index is provided on top of the center layer. The second refractive index is lower than the first refractive index and lower than the third refractive index, such that the conducting bottom layer, the center layer, and the conducting top layer form a slot waveguide. A first electrical connector which connects the second region of the conducting bottom layer with an upper layer is provided.

Abstract: The present invention relates to a slot waveguide formed by a vertical material stack comprising a top layer with a first refractive index, a center layer including a ferroelectric material and with a second refractive index, and a Si1-xGex pseudosubstrate layer with 0<x?1 and with a third refractive index. The center layer is grown on the Si1-xGex pseudosubstrate layer. The second refractive index is lower than the first refractive index and lower than the third refractive index. The slot waveguide can be included in a phase-shifter including two vertically arranged electrodes configured for providing a vertical electrical field (Ev) extending between the top layer and the bottom layer of the slot waveguide and for providing a complementary-metal-oxide-semiconductor compatible driver voltage. The phase-shifter can be configured for providing a linear electro-optical effect inside the center layer of the slot waveguide.

Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

Abstract: A measuring carrier for position-resolved meteorological determination of a measurement variable dependent on the dielectric permittivity of a device under test. The measuring carrier has a supporting means comprising a measuring surface, to which the device under test can be applied, and a measuring transmission line which entirely or partially forms the measuring surface and comprises a multiplicity of transmission line cells for the purpose of transmitting a radio-frequency measurement signal which can be injected at the input port. The measuring surface is structured in a cellular manner, wherein each of the transmission line cells has a cell-individual propagation constant with respect to the radio-frequency measurement signal in a state free of a device under test. This constant differs from the respective cell-individual constants of the other transmission line cells.

Abstract: The invention relates to a gain-control stage (100) for generating gain-control signals (Vc+, Vc?) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (VRef) and a variable gain-control voltage signal (VGC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (V1) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (VC+, VC?) in dependence on the variable gain-control voltage signal (VGC), the reference voltage signal (VRef) and a first biasing current (IB1) that depends on the control voltage signal.

Abstract: A sensor device including a deflectable membrane made of a 2D nanomaterial, a first optical waveguide for guiding light, disposed adjacent to the membrane and extending along the surface of the membrane at least in a first section, as well as a measuring device for measuring, within the first section the influence of the membrane on an evanescent wave range of the light guided along the first optical waveguide. The influence of the membrane on the light guided in the optical waveguide, in particular on the evanescent wave range of the light, can be measured interferometrically by detecting phasing differences or phase shifts. This allows for a force-free readout of the membrane deflection. By using very thin 2D nanomaterials, the membrane can also react to very quick changes in force.

Abstract: Method for producing a semiconductor device by providing a silicon wafer having a plurality of equal height raised portions on a first surface thereof; depositing an etch stop layer on the first surface; planarizing a surface of the etch stop layer; permanently bonding a first carrier wafer on the etch stop layer surface; producing components on or in a second wafer surface in a FEOL process; etching a plurality of trenches into the wafer, each trench formed at the respective location of one of the raised portions; depositing side wall insulation layers on side walls of the trenches; forming through-silicon vias by filling the trenches with electrically conductive material; producing a conductor path stack in a BEOL process for contacting the active components on the second surface; temporarily bonding a second carrier wafer onto a surface of the conductor path stack; removing the first carrier wafer and exposing the vias.

Abstract: The invention relates to an electrooptical device comprising a semiconductor substrate having a front side and a back side, at least one photonic component arranged on the front side of the semiconductor substrate, the photonic component comprising an active layer made of a non-linear optical material, wherein at least one cavity, extends through the semiconductor substrate and connects the active layer on the front side of the semiconductor substrate with the back side of the semiconductor substrate.

Abstract: Novel phase locked loop architectures that can overcome the limitation of the maximum operating frequency of the fractional-N phase-locked loop (PLL) for fast-chirp frequency modulated continuous wave (FMCW) radars are suggested. Several phase frequency detector and charge pumps (PFD&CPs) are put in parallel and are operated with reference signals that are generated by using a delay-locked loop (DLL) instead of further increasing the operating frequency of the PFD&CP. The proposed DLL supported parallel PLL architectures enable further speeding up the FMCW chirp as well as improving its linearity and the performance of Range Doppler Radars based on fast-chirp FMCW radar. Methods for operating the parallel fractional N phase locked loop are proposed.

Abstract: The present invention relates to a phased array antenna (10) with an electronically variable antenna pattern, wherein control signals for at least two phased antenna elements (13) are processed for a broadcast transmission and are broadcast to the phased antenna elements (13) via a wireless medium or using feed lines for useful signal components of the phased antenna elements in a frequency band differing from the frequency band of the useful signal components. As a result of using the broadcast transmission in a different frequency band, there is no need for any additional signals or lines for the array antenna, and the complexity of the array antenna can be reduced and the flexibility and reconfigurability can be improved.

Abstract: A sensor device including a deflectable membrane made of a 2D nanomaterial, a first optical waveguide for guiding light, disposed adjacent to the membrane and extending along the surface of the membrane at least in a first section, as well as a measuring device for measuring, within the first section the influence of the membrane on an evanescent wave range of the light guided along the first optical waveguide. The influence of the membrane on the light guided in the optical waveguide, in particular on the evanescent wave range of the light, can be measured interferometrically by detecting phasing differences or phase shifts. This allows for a force-free readout of the membrane deflection. By using very thin 2D nanomaterials, the membrane can also react to very quick changes in force.

Abstract: The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).

Abstract: A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well region, comprising doped source and drain regions of a second conductivity type and at least one MOS channel region extending between the source and drain regions under a respective gate stack, and a dielectric isolation layer of the STI or LOCOS type and laterally surrounding same, wherein well portions of the well region adjoin the MOS channel region in the two opposite longitudinal directions oriented perpendicular to a notional connecting line extending from the source through the MOS channel region to the drain region, and which extend as far as a surface of the active MOS transistor region, so that the respective well portion adjoining the MOS channel region is arranged between the MOS channel region and the dielectric isolation layer.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A method and system for oversampling a waveform with variable oversampling factor is suggested. The method and for dynamic selection of the oversampling factor are based on a modified equivalent time sampling approach. Multiple waveforms are transmitted, which are separated by a variable delay. The method permits that a receiver selects a different oversampling factor for the received waveform. As a result the method and system provide for oversampling a waveform with a variable, dynamically selectable oversampling factor.

Abstract: A chip antenna comprising at least one emitter which extends parallel to a main surface of a semiconductor substrate supporting the chip antenna, wherein the emitter is arranged on an island-like support zone of the semiconductor substrate, the support zone being surrounded by at least one trench which is completely filled with a gas, the trench passing through the entire depth of the semiconductor substrate and being bridged by at least one retaining web which forms a supporting connection between the support zone and the rest of the semiconductor substrate.

Abstract: A tunable plasmon resonator, comprising a plasmon resonance layer made of graphene, a crystalline group-IV-semiconductor material or a crystalline group-III-V semiconductor material, and arranged on a carrier substrate, the plasmon resonance layer having a plasmon resonance region that is exposed to a sensing volume and a tuning device that is integrated into the plasmon resonator and arranged and configured to modify a density of free charge carriers in the plasmon resonance region or to modify an effective mass amount of the free charge carriers in the plasmon resonance region by applying of a control voltage to tuning control electrode(s) of the tuning device, thereby setting a plasmon frequency of plasmon polaritons in the plasmon resonance region to a desired plasmon frequency value within a plasmon frequency tuning interval, for resonance excitation of plasmon polaritons by incident electromagnetic waves of a frequency corresponding to the set plasmon frequency value.