Abstract: The invention provides in an electron microscopy grid, comprising: a perforated substrate; a support film on the perforated substrate; a mixture of different linker molecules according to Structure (I), wherein AG is an anchoring group, for anchoring the linker molecule to the solid support; BU is a binding unit, for binding to the analyte; L1 is a first linear linker section; L2 is a second linear linker section; ? is the angle between the linear linker section L1 and the linear linker section L2; AS is an angled linker section, connecting the linear linker section L1 and the linear linker section L2. The invention further provides in method of structural determination of analytes, using such EM-grids.

Abstract: A method for forming an interconnection structure (10) for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines (113) above a first and second conductive line (101, 108). At least one of the third conductive lines comprises a contacting portion forming a first via connection (114) to the second conductive line. The method further comprises forming spacers (115) on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole (116) extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection (118) and forming a set of fourth conductive lines (119) extending between the spacers.

Abstract: The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.

Abstract: According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed.

Abstract: The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.

Abstract: A slope analog-to-digital converter, ADC, for converting an analog input signal to a digital representation, said slope ADC comprising: a comparator configured to compare two input signals, wherein a sampled value of the analog input signal and a slope signal are used in forming the two input signals; a memory element, which is configured to receive a trigger signal based on the comparator identifying a change in which of the two input signals is higher, and a counter signal, wherein a value of the counter signal when the trigger signal is received provides the digital representation of the sampled value of the analog input signal; wherein the slope signal and the counter signal have a nonlinear relationship, wherein the nonlinear relationship is adapted to improve linearity of a transfer function of the slope ADC for converting the analog input signal to the digital representation.

Abstract: In one aspect, an optical system is disclosed. In some embodiments, the optical system includes an optical waveguide, and at least two coupling means forming at least one confocal point being located within the optical waveguide, where a first coupling means of the at least two coupling means has a first focal length, and a second coupling means of the at least two coupling means has a second focal length. In some examples, the first coupling means is configured to couple and/or focus incident light to the optical waveguide, and the second coupling means is configured to emit and/or collimate light conveyed by the optical waveguide.

Abstract: Example embodiments describe a computer implemented method for obtaining parameterized characteristics of a tissue comprising obtaining at least two weighted MRI volume scans of the tissue, and transforming the two weighted MRI volume scans into parameters of a parameterized voxel-based model of the tissue by combined performing, by a super-resolution imaging technique, constructing a volume comprising voxels of the parameterized voxel-based model, and, by a quantitative MRI modelling technique, constructing the parameters for the respective voxels of the parameterized voxel-based model.

Abstract: A method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device is disclosed. The MTJ device is switchable between a first resistance state and a second resistance state. A first threshold voltage for switching the MTJ device from the second resistance state to the first resistance state is lower than a second threshold voltage for switching the MTJ device from the first resistance state to the second resistance state. The method includes applying a first voltage pulse across the MTJ device with an amplitude having an absolute value equal to or greater than the first threshold voltage and lower than the second threshold voltage, thereby setting the MTJ device to the first resistance state regardless of whether the MTJ device initially is in the first or second resistance state.

Abstract: A sensor is provided. The sensor includes a field effect transistor comprising: an active region comprising a source region, a drain region, and a channel region between the source region and the drain region; a dielectric region on the channel region; an enzyme coupled to the dielectric region, the enzyme having an active site for interacting with a substrate; an electrolyte-screening layer coupled to the dielectric region, covering part of the enzyme while leaving the active site uncovered, thereby permitting interaction of the substrate with the active site, and a fluidic gate region to which the active site of the enzyme is exposed. A biosensing device including one or more of the sensors is also provided.

Abstract: In an aspect, a mixed metal oxide comprises or consists essentially of: a mixture comprises or consisting essentially of 0.30 to 0.69 parts by mole Mg, 0.20 to 0.69 parts by mole Zn, 0.01 to 0.30 parts by mole of a third element selected from Al and Ga, and, either, when the third element is Al, 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids, or, when the third element is Ga, 0.00 to 0.15 parts by mole of other elements selected from metals and metalloids, wherein the sum of all parts by mole of Mg, Zn, the third element, and the other elements amounts to 1.00, wherein the amount in parts by mole of the other elements is lower than the amount in parts by mole of Mg and is lower than the amount in parts by mole of Zn; oxygen; and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.

Abstract: A flow control system for a microfluidic device includes: a plurality of fluid flow controllers, each fluid flow controller associated with a respective microfluidic device inlet of the microfluidic device, and wherein each fluid flow controller includes: a controller inlet for receiving a fluid flow, a first fluid channel and a second fluid channel, each of the first and the second fluid channels having a first end connected to the controller inlet and a second end connected to a supply channel, and a valve for selecting the fluid flow to be passed from the controller inlet to the first fluid channel or to the second fluid channel, wherein the first fluid channel has a first flow resistance that smaller than a second flow resistance of the second fluid channel.

Abstract: A cooling device configured to be mounted in close proximity to an electronic component that is to be cooled is provided. In one aspect, the device includes impingement channels and return channels for guiding a flow of cooling fluid towards and away from a cooled surface of the electronic component. The device also includes a heat exchanger and a pump, so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels, the return channels, and the heat exchanger are integrated in a common housing, which includes an inlet opening and an outlet opening for coupling the device to a refrigerant loop. The pump may be a micropump mounted directly on the housing and coupled to the inlet and outlet openings in the housing. A cooling system including the device and the refrigerant loop is also provided.

Abstract: A computer-implemented method for exploring, by a table-based parallel reinforcement learning, PRL, algorithm, an unexplored domain comprising a plurality of agents and states, the unexplored domain represented by a state-action space. The method includes the steps performed by one or more of the plurality of agents receiving an assigned partition of the state-action space represented by a table; and executing during a plurality of episodes actions for states within the partition. An action transits a state; and granting to a transited state a reward; and exchanging state-action values with other agents of the plurality of agents in the domain; and updating the table.

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

Abstract: A device for medium access control in a node of a wireless communication network with time-shared medium includes a slot allocation module configured to allocate a timeslot for transmission from the node to a destination node over the time-shared medium; a validation module configured to validate a data packet before transmission to the destination node based on a latency requirement for the data packet, and an expected latency for the data packet based on the position in time of the timeslot, resulting in an approved data packet or a disapproved data packet; a scheduling module configured to schedule an approved data packet in the timeslot for transmission to the destination node.

Abstract: The disclosure relates to a trench capacitor device for a superconducting electronic circuit. The trench capacitor device includes a substrate, a first capacitor electrode, and a second capacitor electrode, each electrode including a superconductor and extending into the substrate. The first electrode is circumferentially enclosed by the second electrode such that an inwardly facing surface of the second electrode faces an outwardly facing surface of the first electrode.

Abstract: A method for forming an intermediate structure in the formation of an optoelectronic device in provided. The method includes: a) obtaining a stack of layers over a substrate holder in a sputtering chamber, the stack of layers comprising an active layer comprising an active material having a perovskite crystal structure, an n-type semiconducting layer comprising a fullerene over the active layer, and an energy alignment layer comprising a lithium halide, a magnesium halide Al2O3 or a metal fluoride on, and in contact with, the n-type semiconducting layer, wherein the energy alignment layer comprises an exposed top surface, and b) sputtering an n-type semiconducting metal oxide layer on the exposed top surface of the energy alignment layer, wherein said sputtering is performed at a sputtering power density of at most 1 W·cm?2 and at a temperature of the stack of layers of at most 100° C.

Abstract: The disclosed technology relates to a magnetic domain wall-based memory device including a combination of at least one magnetic domain wall track and at least one spin orbit torque (SOT) track, which are arranged in a crossing architecture. The SOT track can include a first strip of a patterned SOT generating layer, wherein the first strip extends into a first direction and is configured to pass a first current along the first direction. The magnetic domain wall track can include a second strip of the patterned SOT generating layer and a first magnetic strip of a patterned magnetic free layer, wherein the second strip extends along a second direction and intersects with the first strip in a first crossing region. The first magnetic strip can be provided on the second strip including the first crossing region and can be configured to pass a second current along the second direction.

Abstract: According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs.