Abstract: A semiconductor device comprises a substrate, a first hole-transporting layer over the substrate, a first electron-transporting layer on the first hole-transporting layer, and a second hole-transporting layer over the first electron-transporting layer. At least one of the first electron-transporting layer and the second hole-transporting layer has an organic component. The device is characterized by one of the following: a metal oxide layer present on the first electron-transporting layer, wherein a second electron-transporting layer is on the metal oxide layer, wherein the second hole-transporting layer is on the second electron-transporting layer, or the second hole transporting layer has a first p-doped hole-transporting surface present on the first electron-transporting, layer and a second p-doped hole-transporting surface facing away from the first p-doped hole-transporting surface, or the first electron-transporting layer is on a top surface and on sidewalls of the first hole-transporting layer.

Abstract: A package includes a metal plate and a carrier substrate mounted on the top surface thereof, which includes one or more superconducting chips mounted on the carrier substrate or configured to receive the one or more chips mounted thereon. The carrier substrate and the plate are sandwiched between the planar portions of a first and second magnetic shield structure, at least the first structure including a planar portion and a receptacle-shaped shell portion arranged above and around the chip location. The package includes one or more pillars formed of a magnetic shielding material which are clamped between the planar portions of the shield structures, wherein the one or more pillars are penetrating the carrier substrate and the metal support plate, and wherein the one or more pillars are in physical contact with both of the planar portions.

Abstract: There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.

Abstract: An input circuitry for receiving an analog input signal comprises: an input transistor configured to receive the analog input signal on a gate terminal of the input transistor wherein the input transistor is connected to a digital component providing a digital signal, and wherein the input transistor is configured to receive the digital signal on a bulk terminal of the input transistor; wherein the input transistor is configured to provide an output current based on the analog input signal and the digital signal, such that the input transistor provides digital-to-analog conversion of the digital signal received on the bulk terminal.

Abstract: This patent disclosure relates to an ultrasound transducer including an array of ultrasound transducing elements, a plurality of transducer drive lines. The ultrasound transducer further includes an array of control circuits, wherein each individual control circuit includes a drive switch and a memory element, the drive switch comprising at least one thin-film transistor, the memory element being configured to store and control the state of the drive switch.

Abstract: The present disclosure relates to the determination of a pattern height of a pattern, which has been produced with extreme ultraviolet (EUV) lithography in a resist film. The determination is performed by using an electron beam (e-beam) system, in particular, by using a scanning electron microscope (SEM). In this respect, the disclosure provides a device for determining the pattern height, wherein the device comprising a processor. The processor is configured to obtain a SEM image of the pattern from an SEM. Further, the processor is configured to determine a contrast value related to the pattern based on the obtained SEM image. Subsequently, the processor is configured to determine the pattern height based on calibration data and the determined contrast value.

Abstract: The disclosure includes a system for photoacoustic inspection of an object. The system includes a broadband emission source configured to generate an emission beam, a direction apparatus including at least one spectrum splitter configured to split the emission beam into at least a first and a second component, the direction apparatus being configured to sequentially direct the respective components to N respective locations on the object at N times to generate N respective acoustic waves within the object. The N respective locations and N times are such that the respective N acoustic waves at least semi-constructively interfere to generate a respective propagating acoustic wave within the object. The system also includes a vibration sensing system configured to detect said respective propagating acoustic waves at a respective detection location on the object.

Abstract: According to an aspect there is provided a patterning method comprising: over a lower pattern memorization layer, forming a pattern of first upper blocks, then an upper pattern memorization layer and then a pattern of second upper blocks; thereafter patterning upper trenches in the upper pattern memorization layer using lithography and etching, and forming spacer lines along sidewalls of the upper trenches to define spacer-provided upper trenches, at least a subset being interrupted by a respective first upper block; patterning first lower trenches in the lower pattern memorization layer by etching the spacer-provided upper trenches into the lower pattern memorization layer, at least a subset of the first lower trenches being interrupted by a lower pattern memorization layer portion preserved at a location defined by a respective one of the first upper blocks; thereafter, forming an auxiliary trench mask stack and patterning auxiliary trenches therein using lithography and etching; and thereafter, patterni

Abstract: A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

Abstract: The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

Abstract: The present invention provides a flexible ultrasound transducer (1) for an ultrasound monitoring system for examining a curved object.

Abstract: The present disclosure relates to a method for transferring a target layer to a substrate. The method includes providing a stack by forming a first transfer layer over a first substrate, forming a second transfer layer on the first transfer layer, the second transfer layer being water-soluble, and forming the target layer on the second transfer layer, such that the stack has a top surface. The method also includes bonding the top surface of the stack to a second substrate, separating the first transfer layer from the second transfer layer, and dissolving the second transfer layer in water.

Abstract: A method and apparatus are provided for a spectroscopic measurement for determining a lateral recess depth in the sidewall of a microstructure. The structure is formed on a larger substrate with the sidewall in an upright position relative to the substrate, and the recess extends essentially parallel to the substrate. The recess may be an etch depth obtained by etching a first layer relative to two adjacent layers, the layers oriented parallel to the substrate, the etch process progressing inward from the sidewall. An incident energy beam falling on the structure generates a spectroscopic response captured and processed respectively by a detector and a processing unit. The response comprises one or more peaks related to the material or materials of the substrate and the structure. According to the method, a parameter is derived from said one or more peaks, that is representative of the lateral recess depth.

Abstract: An integrated system for quantum computation is provided, In one aspect, the system includes at least one semiconductor spin quantum bit (qubit); a feedline configured to act as an electron spin resonance (ESR) antenna for control of the at least one qubit; at least one resonator; and a ground plane common to both the feedline and the at least one resonator. The at least one resonator is capacitively coupled to the feedline, and configured for readout of the at least one qubit via the feedline. The feedline and the at least one resonator are arranged in adjacent layers separated by at least a dielectric. A corresponding method of performing quantum computation using such an integrated system is also provided.

Abstract: A microfluidic device (100) comprises: a reaction chamber (102); at least a first and a second supply channel (110a, 110b) for allowing transport of a first fluid and a second fluid, respectively, from a fluid supply source (112a, 112b) into the reaction chamber (102), wherein each of the first and the second supply channels (110a, 110b) comprises a side drain (114a, 114b) connected to the supply channel (110a, 110b) between the fluid supply source (112a, 112b) and the reaction chamber (102), wherein the side drain (114a, 114b) is configured to prevent undesired diffusion of the fluid in the supply channel (110a, 110b) into the reaction chamber (102); at least a first and a second outlet (120a, 120b) connected to the reaction chamber (102) for allowing transport of fluid from the reaction chamber (102), wherein the first and second outlets (120a, 120b) have different dimensions to provide different hydraulic resistance.

Abstract: A method for determining a distance to a target comprises: receiving a bitstream of binary digits corresponding to a time-varying signal based on light transmitted by a light source being reflected by the target, wherein each binary digit in the bitstream is defined based on the time-varying signal at a time instance represented by the binary digit being above or below a threshold; comparing the bitstream to a set of stored reference bitstreams, wherein the set comprises pairs comprising a first reference bitstream and a second reference bitstream representing a common distance to the target, wherein the first reference bitstream is phase-shifted in relation to the second reference bitstream; and determining the distance to the target based on selection of a pair of reference bitstreams based on said comparing.

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.