Abstract: Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.

Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.

Abstract: A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.

Abstract: A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.

Abstract: Tile based interleaving and de-interleaving of row-column interleaved data is described. In one example, the de-interleaving is divided into two memory transfer stages, the first from an on-chip memory to a DRAM and the second from the DRAM to an on-chip memory. Each stage operates on part of a row-column interleaved block of data and re-orders the data items, such that the output of the second stage comprises de-interleaved data. In the first stage, data items are read from the on-chip memory according to a non-linear sequence of memory read addresses and written to the DRAM. In the second stage, data items are read from the DRAM according to bursts of linear address sequences which make efficient use of the DRAM interface and written back to on-chip memory according to a non-linear sequence of memory write addresses.

Abstract: A method of feature matching in images captured from camera viewpoints uses the epipolar geometry of the viewpoints to define a geometrically-constrained region in a second image corresponding to a first feature in a first image; comparing the local descriptor of the first feature with local descriptors of features in the second image to determine respective measures of similarity; identifying, from the features located in the geometrically-constrained region, (i) a geometric best match and (ii) a geometric next-best match to the first feature; identifying a global best match to the first feature; performing a first comparison of the measures of similarity for the geometric best match and the global best match; performing a second comparison of the measures of similarity for the geometric best match and the geometric next-best match; and, if thresholds are met, selecting the geometric best match feature in the second image.

Abstract: Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure. The stored data comprises data defining the regions represented by a plurality of the nodes. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data.

Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.

Abstract: A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.

Abstract: Methods and systems for wirelessly transmitting data between Wi-Fi stations without requiring the Wi-Fi stations to be fully connected to the Wi-Fi network. A first Wi-Fi station generates the data to be transmitted. The data comprises status data and/or wake-up data. The first Wi-Fi station then inserts the data in a vendor-specific information element of a probe request frame and wirelessly transmits the probe request frame. The probe request frame is then received by a second Wi-Fi station. If the probe request frame contains wake-up data and the second Wi-Fi station is operating in a low-power mode when it receives the probe request frame, the second Wi-Fi station will wake-up from the low-power mode. If the probe request frame contains status data then the second Wi-Fi station may process the probe request frame and/or forward at least a portion of the received probe request frame to another device.

Abstract: A method of transmitting data determines a measure of consecutive packet loss in a network; a ratio of a number of data packets and a number of error correction packets is selected in dependence on the measure. A stream of data packets is generated, and a stream of error correction packets is generated in dependence on the stream of data packets such that the proportion of error correction packets generated to the data packets generated is commensurate with the selected ratio.

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

Abstract: Methods and systems for storing a set of two or more variable length data blocks in a memory. Each variable length data block having a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. The methods include: storing, for each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block in a chunk of the memory allocated to that the variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N; storing any remaining portions of the variable length data blocks in a remainder section of the memory that is shared between the variable length data blocks of the set; and storing, in a header section of the memory, information indicating the size of each of the variable length data blocks in the set.

Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.

Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.

Abstract: A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x - C z ? D x D z ? "\[RightBracketingBar]" ? H z ? D x D z + H x . It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to, ? "\[LeftBracketingBar]" C y - C z ? D y D z ? "\[RightBracketingBar]" ? H z ? D y D z + H y . It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to, ? "\[LeftBracketingBar]" C x ? D y D z - C y ? D x D z ? "\[RightBracketingBar]" ? H y ? D x D z + H x ? D y D z .

Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128·64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.

Abstract: A graphics processing system for a head mounted display (or other non-standard projection display) comprises a low latency distortion unit which is separate from a graphics processing unit in the graphics processing system. The low latency distortion unit receives pixel data generated by the graphics processing system using a standard projection and performs a mapping operation to introduce distortion which is dependent upon the optical properties of the optical arrangement within the head mounted display. The distorted pixel data which is generated by the low latency distortion unit is then output to the display in the head mounted display.

Abstract: A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel.

Abstract: Determining whether a ray intersects a 3D axis-aligned box identifies the front-facing plane of the box which intersects the ray at a position furthest along a direction of the ray. Whether the ray intersects the box is determined by whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified. Whether the ray intersects the box is determined without performing a test to determine whether the ray intersects the identified front-facing plane at a position that is no further along the ray than a position at which the ray intersects the back-facing plane in the front-facing plane dimension.