Abstract: A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved.

Abstract: A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.

Abstract: Methods and graphics processing systems render primitives using a rendering space which is subdivided into a plurality of regions. Geometry processing logic performs a geometry processing phase which determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region; and stores data for the primitives which are present in the region, wherein the stored data comprises, for each of the primitives which are determined to totally cover the region, data to indicate total coverage of the region. Rendering logic performs a rendering phase for rendering primitives within the region.

Abstract: A GNSS receiver comprises a memory interface and a vector processor. The vector processor is configured to: receive, via the memory interface, an array comprising a plurality of correlation results stored in a memory, each correlation result associated with a respective combination of possible receiver parameters for the GNSS receiver; process the array to identify a subset of the correlation results in the array; and retain, in the memory, the identified subset and discard, from the memory, those correlation results of the plurality of correlation results not in the identified subset.

Abstract: A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.

Abstract: Systems and method to implement a geometry processing phase of tile-based rendering. The systems include a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.

Abstract: Data processing systems (e.g. image processing systems) and methods are provided for processing a stream of data values (e.g. pixel values). In each of a plurality of iterations, a respective particular data value of the stream is processed by operating on a respective particular subset of data values of the stream. In each iteration: group indication data for at least one group is retrieved and used to define a set of groups into which data values within the particular subset can be grouped; each of the data values within the particular subset is grouped into one of the groups of the set of groups; the particular data value is processed using one or more of the data values of the particular subset in dependence on the classification of the data values into the groups; and group indication data is stored for a group, for use in a subsequent iteration.

Abstract: Ray tracing systems and computer-implemented methods are described for performing intersection testing on a bundle of rays with respect to a box. Silhouette edges of the box are identified from the perspective of the bundle of rays. For each of the identified silhouette edges, components of a vector providing a bound to the bundle of rays are obtained and it is determined whether the vector passes inside or outside of the silhouette edge. Results of determining, for each of the identified silhouette edges, whether the vector passes inside or outside of the silhouette edge, are used to determine an intersection testing result for the bundle of rays with respect to the box.

Abstract: Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.

Abstract: Graphics processing systems and methods provide soft shadowing effects into rendered images. This is achieved in a simple manner which can be implemented in real-time without incurring high processing costs so it is suitable for implementation in low-cost devices. Rays are cast from positions on visible surfaces corresponding to pixel positions towards the center of a light, and occlusions of the rays are determined. The results of these determinations are used to apply soft shadows to the rendered pixel values.

Abstract: Foveated rendering for rendering an image uses a ray tracing technique to process graphics data for a region of interest of the image, and a rasterisation technique is used to process graphics data for other regions of the image. A rendered image can be formed using the processed graphics data for the region of interest of the image and the processed graphics data for the other regions of the image. The region of interest may correspond to a foveal region of the image. Ray tracing naturally provides high detail and photo-realistic rendering, which human vision is particularly sensitive to in the foveal region; whereas rasterisation techniques are suited for providing temporal smoothing and anti-aliasing in a simple manner, and is therefore suited for use in the regions of the image that a user will see in the periphery of their vision.

Abstract: A method and an intersection testing module for performing intersection testing of a ray with a convex polygon in a ray tracing system. The ray and the convex polygon are defined in a 3D space using a space-coordinate system. The ray is defined with a ray origin and a ray direction. A ray-coordinate system is used to perform intersection testing, wherein the ray-coordinate system has an origin at the ray origin, and wherein the ray-coordinate system has three basis vectors. A first of the basis vectors is aligned with the ray direction. A second and a third of the basis vectors: (i) are both orthogonal to the first basis vector, (ii) are not parallel with each other, and (iii) have a zero as one component when expressed in the space-coordinate system. A result of performing the intersection testing is outputted for use by the ray tracing system.

Abstract: A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.

Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.

Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.

Abstract: A data processing device for detecting motion in a sequence of frames each comprising one or more blocks of pixels, includes a sampling unit configured to determine image characteristics at a set of sample points of a block, a feature generation unit configured to form a current feature for the block, the current feature having a plurality of values derived from the sample points, and motion detection logic configured to generate a motion output for a block by comparing the current feature for the block to a learned feature representing historical feature values for the block.

Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.