Patents Assigned to IMEC vzw
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Patent number: 12648213Abstract: A method for forming a stacked transistor device is disclosed, in which a nanosheet field-effect transistor (FET) structure and a fin FET structure are formed. The method comprises forming a first fin structure and a second fin structure from a vertical stack, wherein the second fin structure is arranged above the first fin structure, and wherein the vertical stack comprises a middle layer arranged between the first and second fin structures. The method further comprises forming, from above, a gate structure across a channel region of the second fin structure, forming, from below, a gate structure across a channel region of the first fin structure, and forming source and drain regions for the first and second fin structures.Type: GrantFiled: June 28, 2023Date of Patent: June 2, 2026Assignee: IMEC VZWInventor: Sujith Subramanian
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Patent number: 12648165Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.Type: GrantFiled: June 2, 2023Date of Patent: June 2, 2026Assignee: Imec vzwInventors: Abhitosh Vais, Bertrand Paravais, Guillaume Boccardi, Bernardette Kunert, Yves Mols, Sachin Yadav
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Patent number: 12635263Abstract: A photovoltaic module includes at least one string of solar cells wherein the solar cells are electrically connected in series using a plurality of connecting elements, wherein each connecting element electrically connects a frontside of one of the solar cells of the at least one string with a backside of the neighboring solar cell of the at least one string; a weave of electrically insulating yarns on which the solar cells are positioned; at least one electronic device comprising a first terminal, and a second terminal, wherein the at least one electronic device is fixed to the weave and wherein the first terminal, and the second terminal are respectively electrically connected with the connecting elements at the backsides of neighboring solar cells of the at least one string.Type: GrantFiled: September 12, 2024Date of Patent: May 19, 2026Assignees: IMEC VZW, UNIVERSITEIT HASSELTInventors: Tom Borgers, Jonathan Govaerts
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Patent number: 12635211Abstract: In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dummType: GrantFiled: June 26, 2023Date of Patent: May 19, 2026Assignee: IMEC vzwInventors: Hans Mertens, Sujith Subramanian
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Patent number: 12631934Abstract: A device for dielectric material characterization of a test sample is provided. The device includes a resonator block having a groove at at least one side of the resonator block, wherein the groove comprises at least a first inclined surface and a second inclined surface and is configured to contact the test sample via the first inclined surface and/or the second inclined surface. In this regard, the resonator block is configured to generate a rotational electric field coupled between the first inclined surface and the second inclined surface of the groove and further to propagate the rotational electric field partially or fully through the test sample in order to perform dielectric material characterization of the test sample.Type: GrantFiled: October 18, 2023Date of Patent: May 19, 2026Assignee: Imec vzwInventor: Qingzhong Deng
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Patent number: 12625136Abstract: A device (1) for sensing an analyte, the device (1) comprises at least a sample inlet (10) for receiving a sample, affinity probes (111) selected to have a preferential binding to the analyte, a transducer (11) sensitive to a characteristic of the analyte and/or a label attached to the analyte, the transducer not being a FET transducer, and a desalting unit (13) for desalting the received sample.Type: GrantFiled: December 2, 2021Date of Patent: May 12, 2026Assignee: Imec vzwInventors: Willem Van Roy, Tim Stakenborg, Kris Covens
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Patent number: 12627298Abstract: A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.Type: GrantFiled: February 19, 2024Date of Patent: May 12, 2026Assignee: IMEC VZWInventors: Shun Nagata, Ewout Martens, Jan Craninckx
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Patent number: 12626481Abstract: A method for light field rendering includes: obtaining an n-dimensional mixture model, with n a natural number equal to or larger than 4, of a light field. The model is made of kernels wherein each kernel represents light information and is expressed by parameter values; mathematically reducing the n-dimensional mixture model into a 2-dimensional mixture model of an image given a certain point of view, wherein the 2-dimensional model is also made of kernels; rendering a view in a pixel domain from the 2-dimensional model made of kernels.Type: GrantFiled: May 5, 2021Date of Patent: May 12, 2026Assignees: UNIVERSITEIT GENT, IMEC VZWInventors: Martijn Courteaux, Glenn Van Wallendael, Peter Lambert
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Patent number: 12618152Abstract: In one aspect, a method of depositing a transition metal dichalcogenide is provided. The method includes depositing a layer of the transition metal dichalcogenide on a substrate by a metalorganic chemical vapor deposition process including exposing the substrate to a mixture of reactant gases including a transition metal precursor and a chalcogen precursor. The mixture further includes a gas-phase halogen-based reactant to volatilize transition metal adatoms deposited on the substrate.Type: GrantFiled: October 9, 2023Date of Patent: May 5, 2026Assignees: IMEC VZW, Katholieke Universiteit LeuvenInventors: Benjamin Groven, Vladislav Voronenkov, Dries Vranckx
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Patent number: 12618752Abstract: A collecting device (200) for collecting airborne particles comprises: a first (202) and second layer (220) spaced apart for forming a particle collection chamber (240; 340) therebetween: wherein inlets (210; 310) and outlets (230; 330) are configured for transporting a flow of air (104) into and out of the particle collection chamber (240; 340) and configured for allowing capturing airborne particles by impaction. The collecting device (200) further comprises at least one liquid access port (260; 260a, 260b; 360a-360h) for filling the particle collection chamber (240; 340) with a reagent; and wherein the particle collection chamber (240; 340) comprises at least one side wall (246; 346) for defining flow of the reagent, such that a first portion (248a; 348a) and a second portion (248b; 348b) of the particle collection chamber (240; 340) are arranged on opposite sides of the at least one side wall (246; 346).Type: GrantFiled: April 20, 2022Date of Patent: May 5, 2026Assignee: IMEC VZWInventors: Ahmed Taher, Benjamin Jones, Sophie Roth
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Patent number: 12620550Abstract: A method includes generating, by a SEM, sets of frames corresponding to regions of a microfabrication pattern, for each set of frames, estimating feature data representing edge positions, linewidths, or centerline positions of one or more features of each region of the pattern, and computing a preliminary estimate of a roughness parameter from the feature data. The roughness parameter is indicative of a line edge roughness, a linewidth roughness, or a pattern placement roughness of the one or more features. The method further includes fitting a model equation to the preliminary estimates of the roughness parameter using a model parameter dependent on the number of frames of each set of frames, the model equation relating the model parameter to the roughness parameter; and computing a final estimate of the roughness parameter as an asymptotic value of the fitted model equation.Type: GrantFiled: March 15, 2023Date of Patent: May 5, 2026Assignees: Imec vzw, Katholieke Universiteit LeuvenInventors: Joren Severi, Gian Francesco Lorusso, Danilo De Simone
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Patent number: 12613276Abstract: According to an aspect there is provided an optical monitoring device comprising: a first input for receiving a portion of a first optical signal coupled from a first waveguide into the first input; a second input for receiving at least a portion of a second optical signal coupled into the second input; a mixing unit for controlling combining of the portion of the first optical signal with the at least a portion of the second optical signal into a combined signal at an output from the mixing unit; and at least one photodetector for detecting the combined signal. The optical monitoring device is configured to apply a modulation signal to modulate at least one of a phase of the portion of the first and/or second optical signal, a coupling of the portion of the first and/or second optical signal into the respective input, or an amplitude of the portion of the first and/or second optical signal being transferred into the combined signal.Type: GrantFiled: May 13, 2024Date of Patent: April 28, 2026Assignees: IMEC VZW, Universiteit GentInventors: Wim Bogaerts, Liu Yichen, Yancan Wu
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Patent number: 12610801Abstract: The disclosure relates to a metallization process for an integrated circuit. One example metallization process includes a method for forming an integrated circuit that includes providing a semiconductor structure having two transistor structures, a gate structure, electrically conductive contacts, a first electrically conductive line, a first electrically conductive via, a second electrically conductive via.Type: GrantFiled: December 15, 2022Date of Patent: April 21, 2026Assignee: Imec vzwInventors: Victor Hugo Vega Gonzalez, Bilal Chehab, Julien Ryckaert, Zsolt Tokei, Serge Biesemans, Naoto Horiguchi
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Patent number: 12607605Abstract: A sensor device comprises: a plurality of sensors, wherein each sensor comprises an optical resonance element configured to be affected by a measurand and has a mutually unique optical resonance frequency; the sensors being configured to receive at least one of a first and a second sensor interrogation signals forming a plurality of signal component pairs, wherein a difference in frequency between the frequencies in the signal component pair is different for different signal component pairs; wherein each sensor is configured to modulate an optical intensity of at least one frequency of a mutually unique signal component pair; and a detector, being configured to receive the first sensor interrogation signal and the second sensor interrogation signal, wherein the detector is configured to detect a plurality of mutually unique beat frequencies for detecting a plurality of measurements by the plurality of sensors.Type: GrantFiled: December 7, 2023Date of Patent: April 21, 2026Assignee: IMEC VZWInventors: Fabrice-Roland Lamberti, Roelof Jansen, Xavier Rottenberg, Jon Kjellman
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Patent number: 12602070Abstract: A voltage reference circuit comprises: first transistor, second transistor, first regulating transistor, and second regulating transistor arranged in a stacked connection, wherein first voltage is provided at first node between first and second transistor, second voltage is provided at second node between second transistor and first regulating transistor, third voltage is provided at third node between first and second regulating transistor; wherein first regulating transistor and second regulating transistor are connected to first node and second node, respectively, for compensating changes in first voltage and second voltage, respectively, to maintain stable voltage levels; wherein voltage reference circuit outputs at least one of the first, second or third voltage as a reference voltage.Type: GrantFiled: April 18, 2023Date of Patent: April 14, 2026Assignee: IMEC VZWInventors: Chutham Sawigun, Xiaolin Yang
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Patent number: 12600933Abstract: An electrode unit for performing electroporation of a biological cell is provided, including at least one electrode which can contact a cell. A stimulation unit and an impedance measurement device are connected to the cell, respectively to provide signals to provide cell electroporation and to measure the impedance of the electrode in contact with the cell. Further, a memory stores a predetermined value of an impedance parameter of the biological cell, and it is arranged to be readable by a comparing element. The comparing element is configured to compare the value stored in the memory with a value measured with the impedance measurement device, and to produce an adjustment signal to the stimulation unit, forming a feedback loop. The unit is further configured to apply a further electrical signal for providing electroporation of the cell upon receiving the adjustment signal from the comparing element.Type: GrantFiled: May 21, 2021Date of Patent: April 14, 2026Assignees: IMEC VZW, Katholieke University Leuven, KU LEUVEN R&DInventors: Bastien Duckert, Dries Braeken, Maarten Fauvart
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Patent number: 12595168Abstract: An intermediate structure for a microfluidic device and a method for manufacturing a microfluidic device are provided. The method includes: a) providing a first substrate having a first layer thereon, and a second layer on the first layer; b) forming a first nanopore in the second layer, in such a way that a part of the first layer coincides with a bottom of the first nanopore; c) exposing said part of the first layer to a liquid etchant, thereby forming a cavity under the first nanopore, the cavity having a larger width than a width of the bottom of the first nanopore; d) filling the first nanopore and the cavity with a filling material, thereby forming a first plug; e) forming a bottom fluidic access for the nanopore by removing part of the first substrate and part of the first layer so as to expose the plug; and f) removing the plug, thereby fluidly connecting the bottom fluidic access to the nanopore.Type: GrantFiled: October 10, 2022Date of Patent: April 7, 2026Assignee: IMEC VZWInventors: Simone Severi, Bert Du Bois, Ashesh Ray Chaudhuri
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Patent number: 12598966Abstract: The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.Type: GrantFiled: February 10, 2022Date of Patent: April 7, 2026Assignee: IMEC VZWInventors: Douglas Charles La Tulipe, Anne Jourdain, Gaspard Hiblot
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Publication number: 20260094270Abstract: The present disclosure relates to the field of medical image processing and, more in particular, to a method for determining an anatomical fracture reconstruction based on one or more medical images of a broken bone, and a system configured for the same.Type: ApplicationFiled: September 29, 2023Publication date: April 2, 2026Applicants: Universiteit Antwerpen, IMEC VZW, MORE INSTITUTE VZWInventors: Jan SIJBERS, Femke DANCKAERS, Jana OSSTYN
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Patent number: 12592277Abstract: The disclosed technology relates to a write driver and a method for operating the write driver for a memory device. The write driver is connected to a memory line of the memory device. Multiple memory cells of the memory device are connected to the memory line at different distances from the write driver. The operating method comprises controlling the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells, and controlling the write driver to provide a larger amount of current for accessing a second memory cell of the memory cells. Thereby, the first memory cell is connected to the memory line at a smaller distance to the write driver than the second memory cell.Type: GrantFiled: November 21, 2023Date of Patent: March 31, 2026Assignee: IMEC VZWInventor: Mohit Gupta