Abstract: A charge sensor circuitry comprises: a detector element configured to generate a charge signal at an internal node; wherein the charge sensor circuitry comprises a first transistor comprising a gate for receiving a first control signal and at least one second transistor comprising a first gate connected to the internal node and a second gate for receiving a second control signal; wherein the charge sensor circuitry is configured to, in a first mode, output a first output signal through the first transistor; wherein the charge sensor circuitry is configured to, in a second mode, reset the internal node through the first transistor and output a second output signal through the at least one second transistor.

Abstract: The current disclosure relates to methods and systems for detecting a target molecule in a sample by using identification molecules linked to assay molecules, wherein the assay molecules bind the target, and where the identification molecules are isolated from the sample and run through a nanopore sensor for detecting the target molecule.

Abstract: A memory stack for a VCMA-MRAM device includes a magnetic tunnel junction (MTJ) layer structure, an auxiliary magnetic layer structure including a second hard magnetic layer and an auxiliary magnetic layer, and an interposer layer structure interposing a free layer of the MTJ layer structure and the auxiliary magnetic layer of the auxiliary magnetic layer structure. The interposer layer structure includes a second barrier layer configured to induce a VCMA in the auxiliary magnetic layer and a non-magnetic spacer layer interposing the second barrier layer and the free layer. In response to a first bias voltage exceeding a first threshold voltage across the memory stack, the VCMA induced in the auxiliary magnetic layer causes the auxiliary magnetic layer to be destabilized from a pinned magnetization state with a magnetization oriented along the first direction, and brought to a destabilized magnetization state.

Abstract: A method for forming a solid electrolyte coating on a substrate (1), the method comprising: a. providing a first and a second electrode (3), b. coating a sol-gel precursor solution (4) of the solid electrolyte coating on the substrate (1) and electrically contacting the sol-gel precursor solution (4) with the first and the second electrode, the sol-gel precursor solution (4) being capable of forming a gel in presence of a voltage, and c. generating the voltage across the sol-gel precursor solution (4) via the first and the second electrodes, thereby transforming the sol-gel precursor solution (4) into a gel.

Abstract: A signal sampling circuitry comprises: a plurality of sampling units receiving an input signal for time-interleaved sampling, each sampling unit comprising: a sampling capacitor having a first plate connected to an output of the sampling unit; a first plate switch between the first plate and a first reference voltage, a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to the second plate; wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.

Abstract: A photonic integrated circuit is provided for performing optical transient computing on an RF-modulated optical carrier signal. The photonic circuit includes at least two optical signal processing units, each including a filter device and a delay element for providing a delayed feedback signal to the filter device. The group delay induced by the delay element is in the range from 1 ps to 100 ps and the 3 dB bandwidth of the filter band is less than the inverse of the group delay. The delay element is adapted to spectrally align at least a portion of the filter band with a resonance in the feedback signal and center frequencies of filter bands are offset between 1 GHz and 100 GHz to allow filtering of different portions of the modulated carrier signal spectrum. The signal processing device has a trainable readout circuit.

Abstract: A computer implemented method for training a learning model by a distributed learning system includes computing nodes. The computing nodes respectively implement the learning model and deriving a gradient information for updating the learning model based on training data. The method involves: encoding, by the computing nodes, the gradient information by exploiting a correlation across the gradient information from the respective computing nodes; exchanging, by the computing nodes, the encoded gradient information within the distributed learning system; determining an aggregate gradient information based on the encoded gradient information from the computing nodes; and updating the learning model of the computing nodes with the aggregate gradient information, thereby training the learning model.

Abstract: The disclosed technology relates to a ferroelectric field-effect transistor (FeFET) memory structure. The FeFET memory structure can include a substrate, including an insulator layer; a gate metal layer on the insulator layer; at least one ferroelectric material layer on the gate metal layer; and a layer structure comprising at least one wide bandgap semiconductor layer on the ferroelectric material layer, wherein the layer structure can include: a first section having a first height, and at least one second section having a second height that is smaller than the first height. The FeFET memory structure can further include a drain metal structure which is arranged on the first section of the layer structure, and one or more source metal structures, wherein each source metal structure is arranged on a respective second section of the layer structure.

Abstract: A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.

Abstract: Examples include a method for localizing one or more defects in a semiconductor device. The method includes switching the semiconductor device on and off at a first frequency and switching an irradiating device on and off at a second frequency. The method also includes acquiring images of the semiconductor device and lock-in averaging the images with a first reference signal having the first frequency and a first phase, to obtain amplitudes indicative of temperatures at a surface of the semiconductor device and/or phase signals indicative of a depth location of the one or more defects in the semiconductor device. The method also includes lock-in averaging the images with a second reference signal having the second frequency and a second phase to obtain a topography of the surface of the semiconductor device. The first frequency is different from the second frequency and/or the first phase is different from the second phase.

Abstract: A collecting device (200) for collection of particles and presentation of collected particles for analysis comprises: a first layer (202) and a second layer (220) spaced apart for defining a particle collection chamber (240); wherein the first layer (202) is configured to receive a flow of air (104) carrying airborne particles, wherein the first layer (202) comprises a plurality of inlet nozzles (210) configured to extend through the first layer (202) for transporting the flow of air (104) therethrough; wherein the inlet nozzles (210) are configured to face a first surface (222) of the second layer (220) for capturing airborne particles in the flow of air (104) entering the particle collection chamber (240) by impaction of airborne particles; wherein the collecting device (200) is configured to provide optical access for performing a measurement, based on light, of airborne particles collected in the particle collection chamber (240).

Abstract: The present disclosure relates to a quantum bit (qubit) chip. The qubit chip includes two or more qubit wafers arranged along a common axis and one or more spacer elements. The spacer elements and the qubit wafers are alternately arranged on the common axis. The qubit chip further includes a conductive arrangement configured to electrically connect the two or more qubit wafers, where the conductive arrangement includes at least one superconducting via per each qubit wafer of the two or more qubit wafers and each spacer element of the one or more spacer elements, the at least one superconducting via passing through the qubit wafer or spacer element.

Abstract: The disclosed technology is related to semiconductor components, including a multilayer structure with a plurality of MIM capacitors. The capacitors are realized as an assembly of capacitors in the form of a stack of at least three electrically conductive layers, separated by dielectric layers and formed conformally on a topography defined by a plurality of dielectric pillars distributed on a conductive bottom plate formed on a first level of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate ayers of the stack become available for contacting the layers by via connections.

Abstract: A light modulating array includes a plurality of light modulating elements, where each light modulating element includes a plurality of electrical interconnects and a heater element coupled to the plurality of electrical interconnects and the heater element is configured to receive electrical energy via the plurality of electrical interconnects. Each light modulating element of the device further includes a phase change material implemented proximal to the heater element and an insulator encapsulating the heater element and the phase change material, where the phase change material is configured to exhibit a change in crystal state based on a thermal contribution from the heater element.

Abstract: A conductive oxygen barrier layer, a stack comprising the conductive oxygen barrier layer, and method of forming the stack for a semiconductor device are provided. The method includes providing a semiconductor substrate, forming a conductive electrode layer on the semiconductor substrate, and forming a conductive oxygen barrier layer on the electrode layer, and then forming at least one complex oxide layer on the oxygen barrier layer. The forming of the oxygen barrier layer includes forming a silicon layer on the electrode layer and a platinum layer on the silicon layer. The forming of the at least one complex oxide layer comprises heating to a temperature in a range of 500-700° C. or higher, which results in the oxygen barrier layer comprising an alloy of platinum and silicon.

Abstract: Example embodiments describe a radio device for wireless communication and radar sensing, the radio device including: a transmitter configured to generate a modulated RF signal and to transmit the modulated RF signal via a transmitting antenna; and a receiver configured to receive a modulated RF signal via a receiving antenna and to down-convert the received modulated RF signal. The radio device additionally includes a selector unit configured to provide the receiver with a copy of the transmit modulated RF signal, or, a local oscillator signal for down-converting the received modulated RF signal, thereby enabling wireless communication and radar sensing operation.

Abstract: Examples include a sensor for estimating the operating age of an integrated circuit experiencing performance degradation and a related tamper detection method. The sensor is operable in a regular use mode or in a readout mode and includes a performance monitor responsive to temperature stress and voltage stress, and an anneal monitor responsive to temperature stress. The performance monitor is configured to receive an operating voltage of the integrated circuit when the sensor is operated in the regular use mode. Each anneal monitor is a pre-stressed monitor, and each performance monitor and each anneal monitor is configured to generate an output signal indicative of the performance degradation for the respective monitor when the sensor is operated in the readout mode.

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a three-input OR/MAJ/AND (OMA3) gate. The OMA3 gate includes a first input node inductively coupled to a first input source, a second input node inductively coupled to a second input source, and a third input node inductively coupled to a third input source. The first input source, the second input source, and the third input source are configured to provide single-flux-quantum (SFQ) pulses. The OMA3 gate also includes a plurality of inductors coupled between various input and output nodes. The OMA3 gate includes a plurality of Josephson junctions. Each Josephson junction is coupled between a common node and one of: the first input node, the second input node, the third input node, the first output node, the second output node, or the third output node.

Abstract: According to an aspect of the present inventive concept there is provided a textile device comprising: a first fabric comprising at least one electrically conductive wire; an electronic component, wherein the electronic component is fixated to the first fabric and wherein the at least one electrically conductive wire is electrically connected to the electronic component; wherein the textile device has a transition region at an area of the first fabric arranged laterally from the electronic component; wherein the textile device further comprises a strengthening element at the transition region, wherein the strengthening element comprises: a second fabric arranged around the first fabric; and a thermoplastic material arranged in relation to at least a first portion of the second fabric, wherein the thermoplastic material is arranged around the first fabric and fills a spacing between the first fabric and the second fabric at least in the first portion of the second fabric.

Abstract: Example embodiments relate to methods for continuous photovoltaic cell stringing and photovoltaic cell assemblies. An example method includes providing a foil in a provision direction in a continuous manner. The method also includes cutting at least one slit into the foil along the provision direction. Additionally, the method includes creating at least one slit opening by folding open the foil at a location of the at least one slit. Further, the method includes providing at least one electrically conductive wire near a first surface of the foil along the provision direction aligned with the at least one slit opening in a continuous manner. Yet further, the method includes folding back the foil at the at least one slit opening after the electrically conductive wire provision such that the at least one electrically conductive wire changes its position.