Patents Assigned to IMEC vzw
  • Patent number: 10998413
    Abstract: The disclosed technology relates generally to integrated circuit structures, and more particularly to a semiconductor fin structure having silicided portions. In an aspect, a semiconductor device including a fin structure and a substrate is disclosed. The fin structure includes a first source/drain region, a second source/drain region, and a channel region. The channel region is arranged between the first source/drain region and the second source/drain region to separate the first source/drain region and the second source/drain region in a length direction of the fin structure. The first source/drain region includes a bottom portion and a top portion, wherein the bottom portion of the first source/drain region is fully silicided and the top portion of the first source/drain region is partly silicided.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 4, 2021
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Sylvain Baudot, Geert Van der Plas
  • Patent number: 10991577
    Abstract: A method of forming a semiconductor structure for a III-N semiconductor channel device and a device produced by the method are disclosed. The method includes: (i) forming a buffer structure on a Si-substrate, wherein forming the buffer structure includes: forming a superlattice including at least one superlattice block, each superlattice block including a repetitive sequence of superlattice units, each superlattice unit including a first layer and a second layer formed on the first layer, wherein the first layer is a carbon-doped AlxGa1-xN layer and the second layer is a carbon-doped AlyGa1-yN layer, wherein x and y differ from each other and 0?x?1, 0?y?1, and wherein said at least first and second layers are epitaxially grown at a temperature of 980° C. or lower, and (ii) forming a III-N semiconductor channel layer above the buffer structure wherein the channel layer is epitaxially grown at a temperature of 1040° C. or lower and is grown to a thickness of 1 ?m or smaller.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: April 27, 2021
    Assignee: IMEC VZW
    Inventor: Ming Zhao
  • Publication number: 20210116434
    Abstract: A method and system for inspection of an item, and a use thereof, are presented. The method comprises acquiring a plurality of projection images of an item at a plurality of projection angles for performing a tomographic reconstruction of the item. A plurality of objects are detected in the tomographic reconstruction and each object has a generic shape described by a parametric three-dimensional numerical model. Said detection comprises determining initial estimates of position and/or orientation of each object and at least one geometrical parameter of the three-dimensional model for each object. The initial estimates are iteratively refining by using a projection-matching approach, in which forward projection images are simulated for the objects according to operating parameters of the radiation imaging device and a difference metric between acquired projection images and simulated forward projection images is reduced at each iteration step.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 22, 2021
    Applicants: UNIVERSITEIT ANTWERPEN, IMEC VZW
    Inventors: Jan DE BEENHOUWER, Jan SIJBERS
  • Patent number: 10985200
    Abstract: A method for producing an image sensor comprises: depositing a first back-end-of-line, BEOL, layer above a substrate comprising an array of light-detecting elements, said BEOL layer comprising metal wirings being arranged to form connections to components on the substrate and together with depositing the first BEOL layer, improving planarization of the first BEOL layer by depositing a planarizing metal dummy pattern in the first BEOL layer, wherein a part of the planarizing metal dummy pattern is arranged above a light-detecting element, wherein the planarizing metal dummy patterns is formed from the same material as the metal wirings and is deposited to planarize density of the metal deposited in the first BEOL layer across a surface of the layer and wherein a shape and/or position of the metal dummy pattern above the array of light-detecting elements is designed to provide a desired effect on incident light.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 20, 2021
    Assignee: IMEC VZW
    Inventors: Veronique Rochus, Xavier Rottenberg
  • Patent number: 10985057
    Abstract: A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: April 20, 2021
    Assignee: IMEC vzw
    Inventors: Anne Jourdain, Nouredine Rassoul, Eric Beyne
  • Patent number: 10978000
    Abstract: A method for driving an active matrix display comprising a plurality of pixels, wherein each pixel comprises a drive transistor having a driver gate, is disclosed. The method comprises: receiving information of a desired image to be displayed; determining a compensated voltage for the driver gate for each pixel based on calibration data, wherein the calibration data comprises a set of individual calibration values applying to different pixels, and wherein the compensated voltage compensates for differences between pixels affecting a relation of an intensity of light output by the pixel as function of a difference between the voltage applied to the driver gate and a threshold voltage of the drive transistor; and outputting the compensated voltage for the driver gate for each of the pixels.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 13, 2021
    Assignee: IMEC vzw
    Inventors: Lynn Verschueren, Kris Myny, Jan Genoe, Wim Dehaene
  • Patent number: 10978601
    Abstract: Example embodiments relate to partially translucent photovoltaic modules and methods for manufacturing partially translucent photovoltaic modules. One embodiment includes a method for electrically interconnecting a plurality of thin-film photovoltaic plates. The method includes positioning a plurality of thin-film photovoltaic plates side by side. The thin-film photovoltaic plates are partially translucent or non-translucent. The method also includes providing at least one connection element on a surface of each of the plurality of thin-film photovoltaic plates. The at least one connection element includes a plurality of electrically conductive wires arranged in a grid structure. Further, the method includes physically separating each connection element into a first connection part that includes a plurality of first electrically interconnected, conductive wires and a second connection part that includes a plurality of second electrically interconnected, conductive wires.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 13, 2021
    Assignee: IMEC vzw
    Inventors: Marc Meuris, Tom Borgers, Bart Onsia
  • Patent number: 10978335
    Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 13, 2021
    Assignee: IMEC vzw
    Inventors: Boon Teik Chan, Efrain Altamirano Sanchez, Ryan Ryoung han Kim
  • Patent number: 10972688
    Abstract: A pixel architecture comprises: an absorption layer, which is configured to generate charges in response to incident light; a semiconductor charge-transport layer, which is configured to transport the generated charges through the charge-transport layer, wherein one or more doped regions are arranged in the charge-transport layer, wherein the charge-transport layer comprises a bias region and a charge-dispatch region being associated with the bias region; an electric connection connecting to and providing a selectable bias voltage to the bias region; and at least one transfer gate, wherein the doped regions and the bias region are differently biased for driving transport of the generated charges towards the charge-dispatch region, and for controlling, together with the at least one transfer gate, transfer of charges from the charge-dispatch region to a charge node.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: April 6, 2021
    Assignee: IMEC vzw
    Inventors: Maarten Rosmeulen, Andreas Suss
  • Patent number: 10963603
    Abstract: A method for generating/updating a database of current-voltage characteristic curves is disclosed. This method includes simulating for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a representative current-voltage characteristic curve, and clustering the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: March 30, 2021
    Assignees: Imec vzw, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Francky Catthoor, Maria-Iro Baka, Patrizio Manganiello
  • Patent number: 10965249
    Abstract: A crystal oscillator circuit comprises: a crystal oscillator; and an injection frequency generating circuit, the injection frequency generating circuit being configured to sense a signal of the crystal oscillator and amplify the sensed signal, the injection frequency generating circuit being further configured to inject the amplified signal to the crystal oscillator; wherein the crystal oscillator circuit is configured such that the crystal oscillator receives the amplified signal during an initial start-up period of the crystal oscillator and stops receiving the amplified signal at an end of the initial start-up period.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: March 30, 2021
    Assignee: IMEC vzw
    Inventor: Ming Ding
  • Patent number: 10957575
    Abstract: An integrated circuit chip having fin-based active devices in the front end of line, and an electrical connection between a buried interconnect rail and a contact area on a semiconductor fin, such as an epitaxially grown source or drain contact area of a transistor, is disclosed. In one aspect, the electrical connection is realized without the intervention of a metallization level formed above the active devices in the IC. Instead, an interconnect via is produced between the buried interconnect rail and a lateral portion of the contact area, wherein the lateral portion is directly contacted by a sidewall of the interconnect via. Methods for producing the interconnect via are also disclosed.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: IMEC vzw
    Inventors: Dmitry Yakimets, Anshul Gupta
  • Patent number: 10956993
    Abstract: A computer-implemented method and related device are disclosed for determining a plurality of operating scenarios of an energy system. The method comprises obtaining a plurality of performance measures of the energy system as a function of time corresponding to a plurality of sets of values of input variables. The method comprises clustering the plurality of sets of values of the input variables and the performance measures associated therewith into groups and defining a descriptor for each of the groups. The method also comprises outputting the descriptors of the groups for use in an online prediction or offline estimation of the energy system.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 23, 2021
    Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D
    Inventors: Dimitrios Anagnostos, Francky Catthoor, Johannes Goverde
  • Patent number: 10957793
    Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: March 23, 2021
    Assignee: IMEC vzw
    Inventors: Vasile Paraschiv, Guglielma Vecchio, Anabela Veloso
  • Patent number: 10948444
    Abstract: The present disclosure relates to a sensor and a measuring system and a sensor network that incorporate one or more such sensors. An example sensor could be configured to measure a conductivity of a liquid. The sensor includes a first electrode and a second electrode, each electrode having a surface area, wherein the surface area of the electrodes determines a cell constant of the sensor (Kcell), and wherein at least one of the electrodes is provided with a switching means arranged so that the surface area of the respective electrode can be changed, thereby varying the cell constant (Kcell) of the sensor.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 16, 2021
    Assignee: IMEC VZW
    Inventors: Greja Brom-Verheyden, Marcel Zevenbergen, Martijn Goedbloed
  • Patent number: 10946344
    Abstract: In a first aspect, the present disclosure relates to a method for forming a diamond membrane, comprising: providing a substrate having an amorphous dielectric layer thereon, the amorphous dielectric layer comprising an exposed surface, the exposed surface having an isoelectric point of less than 7, preferably at most 6; seeding diamond nanoparticles onto the exposed surface; growing a diamond layer from the seeded diamond nanoparticles; and removing a portion of the substrate from underneath the diamond layer, the removed portion extending at least up to the amorphous dielectric layer, thereby forming the diamond membrane over the removed portion.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 16, 2021
    Assignees: IMEC VZW, UNIVERSITEIT HASSELT
    Inventors: Rajesh Ramaneti, Giedrius Degutis, Ken Haenen, Marlies Van Bael, Paulius Pobedinskas
  • Patent number: 10944150
    Abstract: A wireless communication device comprises a control unit, an antenna interface, an active wireless transceiver operable together with the control unit and antenna interface, a passive wireless transceiver operable together with the antenna interface and operable by harvesting power from received radio messages. The device is further configured to deactivate the one or more active wireless transceivers and control unit to an inactive state and, subsequently, by the passive wireless transceiver, activate the control unit and an active wireless transceiver to an active state when the passive wireless transceiver receives a message from the antenna interface.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 9, 2021
    Assignees: IMEC VZW, UNIVERSITEIT ANTWERPEN
    Inventors: Maarten Weyn, Philip Ludovic E Sanders
  • Patent number: 10931742
    Abstract: A method to be carried out by an interface element (IE, 510) between a VNF pool (508) and a control entity (520) is disclosed. The VNF pool (508) comprises a plurality of VNF instances (502) including at least a first and second instances. The control entity (520) is configured to control the VNF instances (502) of the pool (508). The method enables the IE (510) to assist in replicating a state of the first VNF instance on the second VNF instance. The method includes steps of obtaining a control message provided from the control entity (520) to the first VNF instance (502), providing the obtained control message at least to the first and to the second VNF instances (502), and providing an acknowledgement of the control message to the control entity (520) when the interface element (510) has an acknowledgement, either explicit or implicit, of both the control message provided to the first VNF instance (502) and the control message provided to the second VNF instance (502).
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: February 23, 2021
    Assignees: Koninklijke KPN N.V., IMEC VZW, Universiteit Gent
    Inventors: Didier Colle, Wouter Tavernier
  • Patent number: 10930750
    Abstract: The disclosed technology is directed to a method of forming a qubit device.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: February 23, 2021
    Assignee: IMEC vzw
    Inventors: Clement Merckling, Nadine Collaert
  • Patent number: 10928305
    Abstract: A sensor device for quantifying luminescent targets comprises a light source, a detector, a modulator, and a processor. The light source is adapted for exciting the luminescent target. The detector is adapted for detecting the luminescence of the luminescent target resulting in a measured signal which comprises a desired signal originating from the luminescent target and a background signal. The modulator is adapted for modulating a physical parameter resulting in a modulation of the desired signal which is different from the modulation of the background signal. The processor is configured to correlate the modulation of the physical parameter with the modulation of the desired signal and/or the modulation of the background signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 23, 2021
    Assignee: IMEC VZW
    Inventors: Peter Peumans, Liesbet Lagae, Willem Van Roy, Tim Stakenborg, Pol Van Dorpe