Patents Assigned to IMEC vzw
  • Patent number: 10593414
    Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include at least a first magnetic bus, a second magnetic bus, and an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 17, 2020
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Adrien Vaysset, Odysseas Zografos
  • Patent number: 10593765
    Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 17, 2020
    Assignee: IMEC VZW
    Inventors: Soon Aik Chew, Steven Demuynck
  • Patent number: 10591672
    Abstract: A photonic integrated circuit comprises an input interface adapted for receiving an optical input signal and splitting it into two distinct polarization modes and furthermore adapted for rotating the polarization of one of the modes for providing the splitted signals in a common polarization mode,. The PIC also comprises a combiner adapted for combining the first mode signal and the second mode signal into a combined signal and a decohering means adapted for transforming at least one of the first mode signal and the second mode signal such that the first mode signal and the second mode signal are received by the combiner in a mutually incoherent state. A processing component for receiving and processing said combined signal is also comprised.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 17, 2020
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Dries Van Thourhout, Andrea Trita
  • Patent number: 10592632
    Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 17, 2020
    Assignee: Imec vzw
    Inventors: Ryan Ryoung han Kim, Jae Uk Lee
  • Patent number: 10592430
    Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: March 17, 2020
    Assignees: Imec vzw, Stitching Imec Nederland, Universidad Complutense de Madrid
    Inventors: Francky Catthoor, Matthias Hartmann, Jose Ignacio Gomez, Christian Tenllado, Sotiris Xydis, Javier Setoain Rodrigo, Thomas Papastergiou, Christos Baloukas, Anup Kumar Das, Dimitrios Soudris
  • Patent number: 10593549
    Abstract: An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 17, 2020
    Assignee: Imec vzw
    Inventor: Frederic Lazzarino
  • Patent number: 10582143
    Abstract: An image sensor comprises: an array (102) of pixels (104) arranged in rows and columns; readout circuitry (110) for reading out image information from pixels (104) in the array (102) of pixels (104); signal lines (112) for providing control signals to the pixels (104) in the array (102) and/or the readout circuitry (110); a programmable sequence controller (114) configured to control the control signals provided on the signal lines (112), said programmable sequence controller (114) comprising: at least one programmable signal controlling state machine (140), which is configured to define a sequence of states and to define control parameters for the states in the sequence, wherein the control parameters include the control signals to be provided on at least one signal line (112) for controlling at least one of a row of pixels (104) or the readout circuitry (110).
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 3, 2020
    Assignee: IMEC VZW
    Inventors: Roeland Vandebriel, David San Segundo Bello
  • Patent number: 10581703
    Abstract: The disclosure relates to a computer-implemented method for controlling on-demand service provisioning in a network, wherein the network comprises resources for providing a service. In the method, a service request is intercepted. At least one network function, indicated as a first network function, required for the service associated with the service request is determined. Then, the first network function is instantiated on a resource in the network for executing the service in the network.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 3, 2020
    Assignees: KONINKLIJKE KPN N.V., NEDERLANDSE ORGANISATIE VOOR TOEGEPAST-NATUURWETENSCHAPPELIJK ONDERZOEK TNO, IMEC VZW, UNIVERSITEIT GENT
    Inventors: Rudolf Strijkers, Shuang Zhang, Jeroen Famaey, Niels Bouten
  • Patent number: 10578490
    Abstract: A spectrometer is provided. The spectrometer may include an image sensor including a pixel array; and a photonics layer disposed on the pixel array and including a plurality of resonators and a plurality of couplers evanescently coupled to the plurality of resonators.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 3, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., IMEC VZW
    Inventors: Tom Claes, Sung Mo Ahn, Woo Chang Lee
  • Patent number: 10573688
    Abstract: The disclosed technology generally relates to magnetic devices, and more particular to a magnetic structure, and a magnetic tunnel junction device and a magnetic random access memory including the magnetic structure. According to an aspect, a magnetic structure for a magnetic tunnel junction (MTJ) device includes a free layer, a tunnel barrier layer, a reference layer, a hard magnetic layer, and an inter-layer stack arranged between the hard magnetic layer and the reference layer. The inter-layer stack includes a first ferromagnetic sub-layer, a second ferromagnetic sub-layer and a non-magnetic spacer sub-layer. The non-magnetic spacer sub-layer is arranged in contact with and between the first ferromagnetic sub-layer and the second ferromagnetic sub-layer and is adapted to provide a ferromagnetic coupling of a magnetization of the first ferromagnetic sub-layer and a magnetization of the second ferromagnetic sub-layer.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 25, 2020
    Assignee: IMEC vzw
    Inventor: Johan Swerts
  • Patent number: 10574255
    Abstract: A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: February 25, 2020
    Assignee: IMEC vzw
    Inventors: Benjamin Hershberg, Jan Craninckx, Ewout Martens
  • Patent number: 10567083
    Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 18, 2020
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Guy Torfs, Johan Bauwelinck, Haolin Li, Laurens Breyne
  • Patent number: 10564362
    Abstract: Embodiments described herein relate to a light coupler, a photonic integrated circuit, and a method for manufacturing a light coupler. The light coupler is for optically coupling to an integrated waveguide and for out-coupling a light signal propagating in the integrated waveguide into free space. The light coupler includes a plurality of microstructures. The plurality of microstructures is adapted in shape and position to compensate decay of the light signal when propagating in the light coupler. The plurality of microstructures is also adapted in shape and position to provide a power distribution of the light signal when coupled into free space such that the power distribution corresponds to a predetermined target power distribution. Each of the microstructures forms an optical scattering center. The microstructures are positioned on the light coupler in accordance with a non-uniform number density distribution.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 18, 2020
    Assignee: IMEC VZW
    Inventors: Xavier Rottenberg, Tom Claes, Dries Vercruysse
  • Patent number: 10566434
    Abstract: The disclosed technology generally relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to semiconductor structures related to a gate-all-around field effect transistor and a fin field effect transistor. In one aspect, a method of forming field effect transistors includes forming in a first region of a substrate a first semiconductor feature and forming in a second region of the substrate a second semiconductor feature. Each of the first and second semiconductor features comprises a fin-shaped semiconductor feature including a vertical stack of at least a first semiconductor material layer and a second semiconductor material layer formed over the first semiconductor material layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 18, 2020
    Assignee: IMEC vzw
    Inventor: Geert Hellings
  • Patent number: 10566236
    Abstract: The disclosed technology generally relates semiconductor devices and more particularly to vertical channel devices and methods of forming the vertical channel devices. According to one aspect, a method of forming a vertical channel device includes forming on a semiconductor substrate a plurality of vertical channel structures. The method additionally includes forming gates, where each of the gates wraps around one of the vertical channel structures. The method additionally includes embedding the gates in a first dielectric layer and exposing top portions of the vertical channel structures. The method additionally includes forming top electrodes on corresponding top portions of the vertical channel structures. The method additionally includes forming sidewall etch barriers on sidewalls of each of the top electrodes. The method additionally includes forming a second dielectric layer covering the first dielectric layer and the top electrodes.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 18, 2020
    Assignee: IMEC vzw
    Inventor: Juergen Boemmels
  • Patent number: 10566250
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 18, 2020
    Assignee: IMEC vzw
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Patent number: 10559677
    Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 11, 2020
    Assignee: IMEC VZW
    Inventors: Shuzhen You, Niels Posthuma
  • Patent number: 10553480
    Abstract: The present disclosure relates to a method for selectively forming a dielectric material on a first area of a top surface of a substrate. In an embodiment, the method involves providing the substrate including the top surface, the top surface including the first area and a second area, the first area having a hydrophilicity characterized by a water contact angle of at least 45° and the second area having a hydrophilicity characterized by a water contact angle of less than 40°. The method also involves providing a precursor aqueous solution on the substrate, the precursor aqueous solution including: a solvent, a dielectric material precursor, a catalyst for forming a dielectric material from the dielectric material precursor, and an ionic surfactant. Further, the method involves removing the solvent.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 4, 2020
    Assignee: IMEC VZW
    Inventors: Murad Redzheb, Silvia Armini
  • Patent number: 10548517
    Abstract: A spectroscopic apparatus and method for analyzing a biological material are provided. The spectroscopic apparatus may analyze a biological material which has an internal non-uniform tissue depending on a position thereof. The apparatus may include at least one detector configured to obtain respective detection spectrums corresponding to a plurality of measurement regions that are at mutually different positions of the biological material, and an information processor to determine whether the measurement regions are normal by mutually comparing the detection spectrums, or converting contribution degrees of data for a specific component of the biological material by differentiating the detection spectrums.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: February 4, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., IMEC VZW
    Inventors: Seongho Cho, Peter Peumans, Woochang Lee
  • Patent number: 10551741
    Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 4, 2020
    Assignees: ASM IP HOLDING B.V., IMEC vzw
    Inventors: Werner Knaepen, Jan Willem Maes, Maarten Stokhof, Roel Gronheid, Hari Pathangi Sriraman