Abstract: The disclosure relates to a semiconductor device structure. The device structure comprises a first and second FETs, each comprising respective S/D structures, a respective channel structure and a respective gate structure. Each S/D structure comprises an S/D body and a set of vertically spaced apart S/D prongs protruding laterally from the S/D body. The S/D prongs of the first and second FETs extend in opposite lateral directions. Each gate structure comprises a gate body and a set of gate prongs protruding laterally from the gate body into spaces between channel layers of the respective channel structures. The gate prongs of the first and second FETs extend in opposite lateral directions.

Abstract: Embodiments for sorting particles are provided that include a microfluidic channel configured to receive a microfluidic flow that comprises a plurality of particles having different characteristics, the microfluidic channel having a plurality of output flow channels, a first detector configured to detect the location of the particles, a plurality of actuators located along the direction of the microfluidic flow and defining a sorting electrode arrangement. The microfluidic device further comprises a controller configured to receive signals from the first detector and to provide force field profiles for each of the plurality of particles, wherein each force field profile comprises a plurality of deflection force settings along the direction of the microfluidic flow. The controller individually addresses the plurality of actuators to generate a plurality of actuation inducing fields along the direction of the microfluidic flow to generate the deflection force settings in the force field profiles.

Abstract: A method for training a local machine learning model is provided. The method includes receiving a scanning electron microscope (SEM) image of semiconductor features. The method additionally includes determining a location and dimensions of a bounding box within the SEM image. The method yet further includes determining, whether a defect feature exists within the bounding box, based on an unsupervised object detection process. The method also includes, if the defect feature exists within the bounding box, receiving positive rewards. The method also includes, if the defect feature does not exist within the bounding box, receiving negative rewards.

Abstract: According to an aspect of the present inventive concept there is provided an imaging system for imaging of a sample, comprising a light source, an interference filter and a detector, the light source generates illumination light of a single wavelength to induce elastic scattering of the light by the sample, the interference filter selectively reduces transmittance of light having an incident angle on the interference filter corresponding to non-scattered light, the detector is configured to detect a two-dimensional representation of the elastically scattered light transmitted by the interference filter.

Abstract: A system for open-path sensing of a property of a fluid in an environment comprises: a sensing light source; a pumping light source for outputting a pumping beam into the environment for inducing a change of light propagation characteristics of the fluid; wherein the system outputs a probing beam and a reference beam into the environment, such that the probing beam has a larger intersection with the pumping beam than the reference beam; wherein a first interferometer detects a phase shift and/or an intensity change of a received probing beam; and wherein a second interferometer detects a phase shift and/or an intensity change of a received reference beam.

Abstract: A method is provided for forming a FET device.

Abstract: Example embodiments relate to alignment-tolerant photonic sensing systems. An example sensing system includes an illumination module for delivery of a light beam. The sensing system also includes a cartridge that includes a photonic sensor chip having a length axis and a width axis. The photonic sensor chip includes a plurality of grating couplers in a first areal portion of the photonic sensor chip. The photonic sensor chip also includes a plurality of sensing sites. Additionally, the photonic sensor chip includes waveguides connecting each grating coupler to a respective sensing site or group of sensing sites of the plurality of sensing sites. Further, the sensing system includes a cartridge holder for releasably receiving and locking the cartridge into a sensing position. The photonic sensor chip is aligned relative to the illumination module up to permitted alignment tolerances when the cartridge is locked into the sensing position.

Abstract: An electric field gradient focusing device is provided that includes: (i) a fluidic channel having an inlet and an outlet for a fluid, (ii) a first actuator configured to induce a fluid flow in the fluidic channel from the inlet to the outlet via AC electroosmosis, and (iii) a second actuator configured to generate a DC electric field gradient along at least part of the fluidic channel.

Abstract: Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.

Abstract: A coated cathode, a device including the coated cathode and methods for preparation thereof is provided. The coated cathode includes: an active material (10) for supplying and storing Li+ ions, an electrically conductive additive (12), and a coating (11), different from the active material (10), that coats surfaces of the active material (10), wherein the coating (11) comprises amorphous halogen-doped titanium oxide, and wherein the coating (11) has a thickness ranging from 1 to 20 nm.

Abstract: A method for forming a FET device is provided.

Abstract: An integrated photonics arrayed waveguide multiplexing/demultiplexing device is disclosed. The device includes an array of waveguides having an incident light waveguide section including a phase correcting region, a transmitted light waveguide section, a tunable reflector, wherein each pair of consecutive waveguides in the array includes a coupler. The coupler configured to combine light from the transmitted light waveguide sections, determine therefrom an optical phase difference between the two consecutive waveguides, and wherein the couplers are further configured to determine therefrom a change in optical path length required for each of two consecutive waveguides to reach a predetermined optical phase difference, and wherein each phase correcting region is configured to apply the change to correct the optical path length of the respective waveguide.

Abstract: A sampling circuit for sampling an analog input signal including: a capacitive means, a reset switch, and a sampling switch; the reset switch and the sampling switch being connected to a signal generator circuit configured to provide periodic reset and sampling control signals to the respective switches for controlling their operation. The respective periodic reset and sampling control signals have equal duty factors and signal periods, and a phase delay with respect to one another being less than the signals' duty factor, thereby forming an overlap period during which the reset switch and the sampling switch remain closed.

Abstract: Embodiments of the present disclosure provide an imaging device for holographic imaging of a sample, the imaging device comprising a light source generating a light beam, a beam splitter splitting the light beam into an object beam along an object beam path and a reference beam along a reference beam path, and a detector. The imaging device defines a sample position. The object beam is propagated through the sample position, and the detector is arranged to prevent non-scattered object light, passing through the sample position without being scattered by the sample, from being incident onto the detector. The reference beam is propagated through the sample position, and the detector is arranged so that non-scattered reference light, passing through the sample position without being scattered by the sample, is incident onto the detector. The detector detects an interference pattern formed by scattered object light and the non-scattered reference light.

Abstract: The present disclosure relates to at least one multilayer structure that is produced on a semiconductor donor wafer, by growing e.g. group III-V material in a cavity formed in a dielectric support layer. A template layer embeds the multilayer structure. The multilayer structure comprises a release layer that is accessible from the sides. The method further comprises the production of a device and the production of conductive paths connected to the device and terminating in a number of contact pads which are coplanar with a first dielectric bonding surface. The donor wafer is then bonded to a carrier wafer. TSV openings are then produced from the back side of the carrier wafer and an etchant is provided for selectively removing layers of the multilayer structure. The etchant is supplied through the TSV openings for the removal of the release layer. The donor wafer is thereby released to form separate semiconductor chips.

Abstract: A method for forming a stacked transistor device is disclosed, in which a nanosheet field-effect transistor (FET) structure and a fin FET structure are formed. The method comprises forming a first fin structure and a second fin structure from a vertical stack, wherein the second fin structure is arranged above the first fin structure, and wherein the vertical stack comprises a middle layer arranged between the first and second fin structures. The method further comprises forming, from above, a gate structure across a channel region of the second fin structure, forming, from below, a gate structure across a channel region of the first fin structure, and forming source and drain regions for the first and second fin structures.

Abstract: A photovoltaic module includes at least one string of solar cells wherein the solar cells are electrically connected in series using a plurality of connecting elements, wherein each connecting element electrically connects a frontside of one of the solar cells of the at least one string with a backside of the neighboring solar cell of the at least one string; a weave of electrically insulating yarns on which the solar cells are positioned; at least one electronic device comprising a first terminal, and a second terminal, wherein the at least one electronic device is fixed to the weave and wherein the first terminal, and the second terminal are respectively electrically connected with the connecting elements at the backsides of neighboring solar cells of the at least one string.

Abstract: In one aspect, a method of forming a semiconductor device including a plurality of stacked transistor devices having a bottom transistor device and a top transistor device can include: forming a plurality of parallel fin structures on a substrate; forming a sacrificial gate across the fin structures; forming bottom source/drain bodies for each bottom transistor device by epitaxy; forming a bottom dummy contact layer covering the bottom source/drain bodies; forming top source/drain bodies for each top transistor device over the bottom dummy contact layer by epitaxy; depositing an insulating material over the bottom dummy contact layer and the top source/drain bodies; replacing the sacrificial gate with a functional gate stack by a replacement metal gate process; patterning holes extending through the insulating material, with each hole exposing an upper surface portion of the bottom dummy contact layer; replacing the bottom dummy contact layer with one or more contact metals, which can include etching the dumm

Abstract: A device for dielectric material characterization of a test sample is provided. The device includes a resonator block having a groove at at least one side of the resonator block, wherein the groove comprises at least a first inclined surface and a second inclined surface and is configured to contact the test sample via the first inclined surface and/or the second inclined surface. In this regard, the resonator block is configured to generate a rotational electric field coupled between the first inclined surface and the second inclined surface of the groove and further to propagate the rotational electric field partially or fully through the test sample in order to perform dielectric material characterization of the test sample.

Abstract: A device (1) for sensing an analyte, the device (1) comprises at least a sample inlet (10) for receiving a sample, affinity probes (111) selected to have a preferential binding to the analyte, a transducer (11) sensitive to a characteristic of the analyte and/or a label attached to the analyte, the transducer not being a FET transducer, and a desalting unit (13) for desalting the received sample.