Abstract: A method of assembling a DC-DC converter includes: attaching first and second discrete power stage transistor dies to a first side of a substrate, the first discrete die including a high-side power transistor and the second discrete die including a low-side power transistor electrically connected to the high-side power transistor to form an output phase of the DC-DC converter; attaching an inductor to the first side of the substrate so as to electrically connect the output phase to a metal output trace on the substrate, the inductor partly covering at least one of the first and the second discrete power stage transistor dies such that each discrete power stage transistor die that is partly covered by the inductor comprises a plurality of pins that are not covered by the inductor; and visually inspecting the plurality of pins uncovered by the inductor.

Abstract: Methods, devices, and circuits are disclosed regulating a first parameter of one or more LEDs. The methods, devices, and circuits may further be disclosed switching, in response to an indication of a dimmer interface, from regulating the first parameter of the one or more LEDs to regulating a second parameter below a light generation threshold of the one or more LEDs, and switching from regulating the first parameter to regulating the second parameter causes the one or more LEDs to enter a non-light generation mode.

Abstract: A device authenticates accessories by detecting that an accessory is attached to the device, determining a unique identification (ID) for the accessory, determining, based on the unique ID, if the accessory has been paired to the device, and in response to determining that the accessory has been paired to the device, enable use of the accessory by the device. In response to determining the accessory has not been paired to the device, the devices performs a secondary authentication process on the accessory.

Abstract: In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal.

Abstract: A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Abstract: A first power transistor of a DC-DC converter is connected between a voltage supply node and a common node, a second power transistor is connected between a reference node and the common node, and an inductor is connected between the common node and the output node of the DC-DC converter. A controller switches the first transistor off and the second transistor off during a step-down event at the load if current in the inductor exceeds a positive threshold value.

Abstract: An LED driver includes a transformer, current control loop and current adjustment circuit. The primary side of the transformer transfers energy to the secondary side of the transformer responsive to an input signal. The secondary side delivers output current to one or more LEDs at a magnitude corresponding to the amount of energy transferred to the secondary side. The current control loop controls current in the primary side so that the output current equals a reference current signal. The current adjustment circuit injects a current adjustment signal into the current control loop responsive to a phase-cut signal which removes a portion of the input signal. The current control loop also decreases the current in the primary side responsive to the current adjustment signal so that a brightness of each LED connected to the secondary side is decreased by an amount corresponding to the magnitude of the current adjustment signal.

Abstract: A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side.

Abstract: A switching regulator includes a power stage and a controller. The power stage is operable to produce an output voltage. The controller is operable to set a duty cycle for the power stage based on feed-forward control so that the power stage produces the output voltage as a function of an input voltage and a reference voltage provided to the switching regulator. The controller is further operable to adjust the feed-forward control to counteract the effect of one or more nonlinearities of the switching regulator on the output voltage.

Abstract: A symmetric Doherty amplifier includes a main amplifier and a peaking amplifier of the same size as the main amplifier. The symmetric Doherty amplifier is configured to operate at peak output power when the main amplifier and the peaking amplifier are each in saturation, and at output-back-off (OBO) when the main amplifier is in saturation and the peaking amplifier is not in saturation. Phase shift circuitry is configured to shift the phase at an output of the peaking amplifier at OBO so that a load impedance seen by the main amplifier and efficiency of the symmetric Doherty amplifier both increase at OBO as a function of the phase shift at the peaking amplifier output.

Abstract: A switching regulator includes an output phase having a high-side transistor and a low-side transistor operable to switch on and off at different periods responsive to a pulse width modulation (PWM) signal applied to the output phase, each cycle of the PWM signal having an on-portion and an off-portion. The switching regulator further includes a current sense circuit operable to sense the current of the low-side transistor, an analog-to-digital converter operable to sample the sensed low-side transistor current during the off-portion for each PWM cycle and a current estimator operable to estimate a cycle average current for the present PWM cycle based on the low-side transistor current sampled during the off-portion for the immediately preceding PWM cycle and a pulse width estimate for the on-portion for the present PWM cycle.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off.

Abstract: A three way wideband Doherty amplifier circuit includes a first peaking amplifier operable to turn on at a first power level, a second peaking amplifier operable to turn on at a second power level below the first power level and a main power amplifier operable to turn on at all power levels. The main power amplifier has a high impedance load modulated state when the first and second peaking amplifiers are turned off. The three way wideband Doherty amplifier circuit further includes a constant impedance combiner connected to an output of each amplifier. The constant impedance combiner has a characteristic impedance which matches the impedance of the main amplifier in the high impedance load modulated state with or without an output matching device connecting the main amplifier output to the constant impedance combiner, as viewed from the output of the main amplifier.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.

Abstract: A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features.

Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.

Abstract: A circuit includes a power circuit and a current sensing circuit. The power circuit has a main current loop. The current sensing circuit is spaced apart from and electrically decoupled from the power circuit. The current sensing circuit is operable to generate a voltage proportional to an electromagnetic field generated responsive to a current change in the main current loop of the power circuit and generate a current information signal based on the voltage. The current information signal describes the current in the main current loop.