Abstract: One embodiment of the present invention relates to a method of communicating in a network with a plurality of nodes. In the method, information is gathered from the plurality of nodes, where information from each node specifies other nodes from which the node detected messages. Based on the gathered information, a transmit sequence according to which the plurality of nodes are to transmit is determined. Other methods and devices are also disclosed.

Abstract: A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell.

Abstract: An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.

Abstract: A system and method for controlling a device. Data that was encrypted using a first encryption scheme is decrypted, then re-encrypted using a second encryption scheme. The re-encrypted data is then decrypted.

Abstract: A system and method for transferring information include generating a public/private key pair for programming equipment and sending the programming equipment public key to a certificate authority. A programming equipment certificate is generated using the programming equipment public key and a private key of the certificate authority. The programming equipment certificate and a certificate authority certificate are sent to the programming equipment. Information is transferred to or from the programming equipment in response to an authentication using the programming equipment certificate and the certificate authority certificate.

Abstract: One embodiment of the present invention relates to a method for communicating over a multi-carrier communication channel. In the method, sub-carrier frequencies that are reserved for communication between a pair of nework nodes are associated with different sub-carrier groups, where the sub-carriers of each sub-carrier group are assigned a common transmission characteristic that is independent of the transmission characteric for the other sub-carrier groups. Other methods and devices are also disclosed.

Abstract: Methods and systems for transferring information to a device include assigning a unique identifier to a device and generating a unique key for the device. The device is located at a first site, and the unique identifier is sent from the device to a second site. The unique key is obtained at the second site, and it is used for encrypting information at the second site. The encrypted information is sent from the second site to the device, where it can then be decrypted.

Abstract: A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC structure such that it fills the vias formed therein. The method also includes steps of forming a masking structure layer over the OPL, forming an opening in the masking structure that has a critical dimension (CD) smaller than an opening design dimension, anisotropic etching the OPL such that sidewall of the via remains covered with the OPL while forming a trench, and removing any remaining OPL on the sidewalls and trench, wherein the undercut of the sidewalls with respect to the hard mask is minimized by the covering of OPL during the anisotropic etching process.

Abstract: Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.

Abstract: A system and method for frame detection and generation. Each incoming clock-data stream is divided into two independent data streams: a clock path which preserves the timing of the individual clock domains and a data path which multiplexes an arbitrary number of data streams onto a parallel path. A framer array structure implements a context swap and synchronizes the data streams.

Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

Abstract: There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block.

Abstract: One embodiment relates to a network. The network includes a first splitter having an input port and N output ports. A first network node is associated with a first of the N output ports. A second network node is associated with a second of the N output ports and is adapted to receive signals communicated from the first network node through the first splitter. Other apparatuses and methods are also set forth.

Abstract: A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.

Abstract: A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material.

Abstract: A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.

Abstract: A synchronous DRAM (SDRAM) terminates a write operation in response to detecting deactivation of a data strobe signal applied to it during the write operation. In one example, the SDRAM comprises a buffer circuit and an early write termination circuit. The buffer circuit is configured to sample input data responsive to a data strobe signal applied to the SDRAM during a write operation and direct the input data to one or more memory cells of the SDRAM for storing the input data. The early write termination circuit is configured to terminate the write operation at less than a programmed burst length by disabling access to one or more of the memory cells after storage of the sampled input data responsive to detecting deactivation of the data strobe signal.

Abstract: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.