Abstract: A Hall sensor apparatus has a Hall effect field with at least five contacts which are wired to at least five connections, wherein none of the at least five contacts is wired to more than one of the at least five connections, a supply circuit and a measurement circuit. In a first operational phase, a supply current enters the Hall effect field or leaves the Hall effect field through one single connection of the at least five connections, and two differential signals are measured at different common-mode potentials in each case between two of the at least five connections. The measurement circuit is designed to combine the measured differential signals into a total signal.

Abstract: A current sensor device may include a routable molded lead frame that includes a molded substrate. The current sensor device may include a conductor and a semiconductor chip mounted to the molded substrate. The semiconductor chip may include a magnetic field sensor that is galvanically isolated from the conductor by the molded substrate and is configured to sense a magnetic field created by current flowing through the conductor. The current sensor device may include one or more leads configured to output a signal generated by the semiconductor chip. The one or more leads may be galvanically isolated from the conductor by the molded substrate.

Abstract: A power supply includes a reference voltage generator circuit, a ramp generator circuit, and control circuitry. During operation, the reference voltage generator circuit compares a magnitude of a received output voltage feedback signal to a received reference voltage. Based on the comparison, the reference voltage generator circuit produces a varying reference voltage and outputs it to the ramp generator circuit. As its name suggests, a magnitude of the varying reference voltage varies over time. The ramp generator circuit produces a ramp voltage signal, a magnitude of which is offset by the varying reference voltage. To maintain an output voltage of the power supply within regulation, the control circuitry receives the varying reference voltage and controls activation of a power converter circuit to power a load based on a comparison of the ramp voltage signal and the output voltage feedback signal of the power supply.

Abstract: A method and an electronic circuit are disclosed. The method includes detecting at least one operating parameter in an electronic circuit that includes a monitored LED string; adjusting a voltage threshold based on the at least one detected operating parameter; detecting a string voltage across the monitored LED string; comparing the string voltage with the voltage threshold; and detecting a defect in the LED string based on the comparing.

Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.

Abstract: A portable device includes a microphone structure for converting a received audio signal into an electronic signal representing the received audio signal and for transceiving an ultrasonic wave by transmitting the ultrasonic wave and by receiving a reflection of the ultrasonic wave. The portable device includes a control unit for evaluating the reflection of the ultrasonic wave to obtain an evaluation result and for controlling an operation of the portable device based on the evaluation result.

Abstract: A semiconductor device includes a semiconductor body and a first portion including silicon and nitrogen. The first portion is in direct contact with the semiconductor body. A second portion including silicon and nitrogen is in direct contact with the first portion. The first portion is between the semiconductor body and the second portion. An average silicon content in the first portion is higher than in the second portion.

Abstract: Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

Abstract: A sensor module includes a window structure configured to permit the passage of transmitted light and received light between an inside of the sensor module and a field-of-view; a transmitter configured to transmit a transmit light beam; a scanning structure configured to rotate about at least one scanning axis, the scanning structure configured to receive the transmit light beam from the transmitter and direct the transmit light beam towards the window structure and the field-of-view; a light detector configured to detect a reflected light beam that corresponds to the transmit light beam; and at least one processor configured to measure a time-of-flight of a round trip light beam comprising of the transmit light beam and the reflected light beam, compare the time-of-flight to a threshold time, and detect a dirt formation on the window structure on a condition that the time-of-flight is less than the threshold time.

Abstract: An oscillator control system includes an non-linear oscillator structure configured to oscillate about an axis; a driver circuit configured to generate a driving signal to drive the oscillator structure; a detection circuit configured to measure an angle amplitude and a phase error of the oscillator structure; an amplitude controller configured to generate a reference oscillator period based on the measured angle amplitude; a period and phase controller configured to receive the reference oscillator period and the measured phase error from the detection circuit, generate at least one control parameter of the driving signal based on the reference oscillator period and the measured phase error, and determine a driving period of the driving signal based on the reference oscillator period and the measured phase error. The driver circuit is configured to generate the driving signal based on the at least one control parameter and the driving period.

Abstract: A sensor system and an alerting unit. The sensor system according to the invention may comprise first sensing element configured to measure a first signal indicative of a velocity of a movement of an object and a second sensing element configured to measure a second signal indicative of a direction of the movement, further comprising an alerting unit configured to issue a warning if a predefined relationship between the first signal and the second signal is being violated. The invention further teaches an alerting unit configured to monitor a predefined relationship between a first signal and a second signal and further configured to issue a warning should the predefined relationship become violated.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

Abstract: A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate that one or more of the power stages is faulty and disabled; communicate the throttling signal to the processor over a physical line running between the processor and the controller; and place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load. A corresponding method of operating a fault-tolerant power distribution system is also described.

Abstract: Techniques (e.g., implemented in devices, methods and/or in non-transitory storage units) are used for confining wavelengths, e.g., using a pillar photonic crystal. A semiconductor device includes a pillar photonic crystal including a structure and a plurality of pillars extending from the structure in a height direction, wherein the plurality of pillars form at least one waveguide for electromagnetic radiation at a specific wavelength, the at least one waveguide extending in at least one planar direction, wherein the structure includes a confining layer in doped semiconductor material to support propagation of surface plasmon polaritons.

Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

Abstract: A molding compound and a semiconductor arrangement with a molding compound are disclosed. The molding compound includes a matrix and a filler including filler particles. The filler particles each include a core with an electrically conducting or a semiconducting material and an electrically insulating cover.

Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

Abstract: A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface for a processor at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is within an operating range of the processor and below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.

Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.

Abstract: In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.