Abstract: A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.

Abstract: An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.

Abstract: Method for measuring and compensating skews of data transmission lines connecting at least one data transmission device with a data reception device via a parallel data bus comprising for each data transmission line the following steps: measuring the relative time delay of the data transmission line by transmitting a determined sequence of measurement vectors (MV) each consisting of an alternating bit pattern via said data transmission line, wherein the bit alternation frequency is halfed with every transmitted measurement vector (MV); comparing the received measurement vectors (MV?) transmitted via said data transmission line with corresponding reference vectors (RV) stored in said data reception device; shifting the received measurement vectors by inserting data unit intervals (UI) until a received measurement vector (MV?) matches a corresponding reference vector (RV); calculating a relative skew of the data transmission line depending of the number of inserted data unit intervals (UI) with respect to a slo

Abstract: A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm?3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

Abstract: A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission. Provision is made of a test signal generating device for generating test signals used to test the data storage medium. The data storage medium can be switched into a test mode in which the test signals are used for the test.

Abstract: A semiconductor device includes a completed semiconductor chip and a dielectric layer overlying the completed semiconductor chip. A redistribution layer overlies the completed semiconductor chip and is embedded in the dielectric layer. The redistribution layer includes a plurality of microstrip conductors. Each microstrip conductor has a height and a width selected such that the height is at least twice the width. In addition, each microstrip conductor is separated from an adjacent microstrip conductor by a spacing distance that is at least twice the width.

Abstract: A system and method for determining the temperature of a semiconductor wafer at the time of thermal contact of the semiconductor wafer with a temperature sensing element. According to the invention, a temperature profile of the temperature sensing element is recorded from the time of thermal contact up to the time of thermal equilibrium between the semiconductor wafer and the temperature sensing element and the temperature of the semiconductor wafer at the time of thermal contact is determined on the basis of a time period between the time of thermal contact and the time of thermal equilibrium and the temperature TG of the semiconductor wafer reached at the time tG of thermal equilibrium is determined by back calculation with the aid of an equation derived from Newton's law of cooling.

Abstract: Receiver for Receiving Data Frames. According to one aspect, a receiver for receiving data frames which contain information data includes a signal input. Further, the receiver includes a data frame separator circuit for separating the signaling data from the information data. A switching device connects the data present at current input to a data output. A channel decoding circuit decodes the data which is present and generates signals which indicate whether the decoding has been carried out correctly. When correct decoding has taken place, a control circuit buffers all data and outputs a signal to the switching device to connect the buffered information data to the channel decoding circuit. When the signal indicates the correct decoding is received, the control circuit outputs the decoded information data.

Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.

Abstract: The present invention relates to semiconductor devices. According to the present invention a semiconductor device is described, comprising: a substrate for carrying a semiconductor chip on a first surface of said substrate; said semiconductor chip being punctually attached to said substrate on said first surface of said substrate via a single attachment point; and means for protecting said semiconductor chip on said first surface of said substrate at least protecting said semiconductor chip laterally.

Abstract: The present invention relates to a process for producing a porous layer adhering to a substrate, which comprises the steps: a. preparation of a composition comprising an organic polymer constituent and an inorganic-organic constituent and/or an inorganic constituent, b. application of this composition to a substrate and formation of a layer on the substrate, and c. removal of the inorganic-organic constituent and/or the inorganic constituent from the layer to form a porous layer adhering to the substrate.

Abstract: The invention relates to an apparatus and a method for ascertaining and correcting the optimum sampling time for an oversampled input bit stream. This involves feeding the data bit blanked with the current sampling phase into the comparative sequence and using the data bit to ascertain a new, corrected sampling phase. This decision-based approach enables the sampling phase to be continuously corrected.

Abstract: The invention relates to a semiconductor component for mounting on a printed circuit board. The semiconductor component includes a housing that at least partially surrounds at least one flat semiconductor chip. Electrical contacts are assigned to the semiconductor chip and serve to establish an electrical connection to electrodes provided on a printed circuit board. The flat semiconductor chip has a mounting lateral surface that includes contact surfaces configured to make contact with the electrical contacts. A buffer layer is located between the housing and the chip, and surrounds the chip up to a supporting surface located on the mounting lateral surface.

Abstract: The energy consumption of a static memory cell, which may be connected to a first bit line and a second bit line of a bit line pair by means of transistors, is reduced in an energy-saving mode of operation by adjusting the potentials on each of the bit lines of the bit line pair such that a potential difference between the gate terminals of the transistors and the bit lines of the bit line pair is reduced in comparison with a normal mode of operation.

Abstract: A blank and a semiconductor device are include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.

Abstract: A system having a signal processor for detection of a signal type of a signal has a processor is disclosed. One embodiment is designed to determine a first variable which is characteristic of a first spectrum element of the signal spectrum, and to determine a second variable which is characteristic of a second spectrum element of the signal spectrum, a system for determination of a ratio between the first variable and the second variable, and a detector which is designed to detect the signal type on the basis of the ratio.

Abstract: Method of fabricating an integrated memory device including the steps of providing a semiconductor substrate, including an array region and a support region; providing GC-lines in said array region and in said support region, wherein the GC-lines in said support region have a first height; providing in the array region bit line contacts projecting above said GC-lines, wherein said bit line contacts have a second height being higher than said first height; providing a first isolation layer, the maximum height of said GC-lines in said support region including the coverage of said first isolation layer being lower than said second height; providing a second isolation layer on said first isolation layer; and polishing said first isolation layer and said second isolation layer, such that a planar surface of the integrated memory device is provided and such that said bit line contacts are exposed.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises an at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: Bipolar power semiconductor component comprising a p-type emitter and more highly doped zones in the p-type emitter, and production method The invention relates to a bipolar power semiconductor component comprising a semiconductor body (1), in which a p-doped emitter (8), an n-doped base (7), a p-doped base (6) and an n-doped main emitter (5) are arranged successively in a vertical direction (v). The p-doped emitter (8) has a number of heavily p-doped zones (82) having a locally increased p-type doping. The invention furthermore relates to a method for producing a power semiconductor component.

Abstract: A divider circuit comprises at least two clock edge controlled differential buffer store elements, each being clocked by complementary input clock signals, each comprising internal storage nodes which are pre-chargeable to a pre-charge potential, and each comprising a differential data input. The internal storage nodes of the buffer store elements are either pre-charged at the pre-charge potential or store a logic level, depending on the relevant input clock signals. The differential data inputs of one of the buffer store elements is connected to the internal storage nodes of the other buffer store element and pulsed signals can be tapped off at the internal differential storage node.