Patents Assigned to INFINEON
  • METHOD AND APPARATUS FOR WRITING TO A TARGET MEMORY PAGE OF A MEMORY
    Publication number: 20070214329
    Abstract: A method and apparatus for writing to a target memory page of a memory has an initial memory page having allocated thereto a marking memory containing information whether a content of the initial memory page is written correctly to the target memory page. The apparatus includes a memory controller for determining whether the target memory page has an error, if the target memory page has an error, for erasing it, if the marking memory indicates that the target memory page is not written correctly, for writing the target memory page based on the initial memory page, if the target memory page is written correctly, for changing the marking memory such that the marking memory indicates that the target memory page is written correctly, and if the marking memory of the initial memory page indicates that the target memory page is written correctly, for erasing the initial memory page.
    Type: Application
    Filed: February 28, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: WIELAND FISCHER
  • DYNAMICALLY RECONFIGURABLE UNIVERSAL TRANSMITTER SYSTEM
    Publication number: 20070213062
    Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus; and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.
    Type: Application
    Filed: May 14, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joel Medlock, Uma Jha, David Holmes, Andrea Chen, Madasamy Kartheepan
  • COMMUNICATION DEVICE, RADIO COMMUNICATION ARRANGEMENT AND METHOD FOR TRANSMITTING INFORMATION
    Publication number: 20070211624
    Abstract: A radio communication device having a first radio transmission unit for transmitting information according to a first radio transmission technology as well as a second radio transmission unit for transmitting information according to a second radio transmission technology. In addition, the radio communication device has a selection unit for selecting the first radio transmission unit or the second radio transmission unit or both radio transmission units for transmitting information depending on at least one predefinable radio transmission technology selection criterion.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Andreas Schmidt, Norbert Schwagmann, Martin Hans
  • Method of producing a topology-optimized electrode for a resonator in thin-film technology
    Publication number: 20070209174
    Abstract: In a method of producing an electrode for a resonator in thin-film technology, the electrode of the resonator is embedded in an insulating layer such that a surface of the electrode is exposed, and that a surface defined by the electrode and the insulating layer is substantially planar.
    Type: Application
    Filed: July 9, 2004
    Publication date: September 13, 2007
    Applicant: Infineon Technologies AG
    Inventors: Robert Aigner, Luder Elbrecht, Stephan Marksteiner, Winfried Nessler
  • Circuit with an arrangement for the detection of an interrupted connecting line
    Publication number: 20070210803
    Abstract: A circuit arrangement is disclosed herein comprising a first and a second supply terminal for application of a supply voltage and an output terminal for providing an output signal. The circuit arrangement additionally comprises at least one programmable switch arrangement comprising a normally off MOS transistor, which has a load path between a first and second load terminal and a control electrode, and comprising a capacitive component, having a first and a second terminal, the first terminal of which is connected to the control electrode of the MOS transistor and the second terminal of which is connected to a control and programming terminal. In this case, the load path of the MOS transistor is connected between the output terminal and one of the supply terminals.
    Type: Application
    Filed: February 22, 2007
    Publication date: September 13, 2007
    Applicant: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • INTEGRATED CIRCUIT HAVING A WORD LINE DRIVER
    Publication number: 20070211531
    Abstract: An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to each sector.
    Type: Application
    Filed: February 14, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Massimo Atti, Michele Boraretto, Christoph Deml, Maciej Jankowski
  • Resistive Memory Arrangement
    Publication number: 20070211515
    Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Corvin Liaw, Thomas Roehr, Michael Kund
  • METHOD FOR DETERMINING AN EDGE PROFILE OF A VOLUME OF A PHOTORESIST AFTER A DEVELOPMENT PROCESS
    Publication number: 20070212624
    Abstract: The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the photoresist is divided into cells. A chemical master equation is set up which reflects the stochastic kinetics of chemical reactions proceeding in cells of the volume of the photoresist during the development process. The chemical master equation is solved for a given development time on the basis of a Gillespie algorithm in order to determine developed and non-developed cells of the volume of the photoresist at the end of the development process. Finally, the edge profile of the volume of the photoresist after the development process is determined on the basis of a cluster of non-developed cells.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Alexander Philippou, Thomas Mulders
  • Substrate with Strip Conductors and Production of Strip Conductors on Substrates for Semiconductor Components
    Publication number: 20070210883
    Abstract: A substrate including strip conductors with a wiring pattern that connects contact areas to one another. The strip conductors have a small strip conductor width. The contact areas and/or the strip conductors form a narrow connection pitch and include electrically conductive carbon nanotubes.
    Type: Application
    Filed: January 22, 2007
    Publication date: September 13, 2007
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Gottfried Beer, Jochen Dangelmaier, Alfred Haimerl, Manfred Mengel, Klaus Mueller, Klaus Pressel
  • Flexible rewiring plate for semiconductor components, and process for producing it
    Patent number: 7268423
    Abstract: The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 ?m, which rewiring plate includes a base body and passages with carbon nanotubes, the lower end of the passages opening out into contact connection surfaces, and the carbon nanotubes forming an electrically conductive connection from the contact connection surfaces to the front surface of the base body.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Jochen Dangelmaier, Alfred Haimerl, Manfred Mengel, Klaus Mueller, Klaus Pressel
  • Microprocessor configuration with encryption
    Patent number: 7269742
    Abstract: A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Oliver Kniffler, Holger Sedlak
  • Capacitor and method of manufacturing a capacitor
    Patent number: 7268383
    Abstract: Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth, Erdem Kaltalioglu
  • Method and apparatus for orienting semiconductor wafers in semiconductor fabrication
    Patent number: 7268877
    Abstract: Described are systems and methods for orienting a semiconductor wafer during semiconductor fabrication with the aid of an optical alignment system, the semiconductor wafer having an alignment mark with regular structures, on the basis of which the position of the semiconductor wafer can be determined.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventor: Jens Stäcker
  • Systems, methods and computer program products for leakage-proof program partitioning
    Patent number: 7269671
    Abstract: Systems, methods and computer program products partition a whole program when it does not fit in a device's memory. Minimal, safe program partitions are downloaded from the server on demand into the embedded device just before their execution. Code and data of the program are partitioned such that no information regarding the control flow behavior of the program is leaked out. Thus, by observing the program partitions that are downloaded from the server to the device, an attacker is unable to guess which branches are taken in the program and what is the control flow of the program. This property of tamper resistance is valuable for secure embedded devices, such as smart cards, which could hold sensitive information and/or carry out critical computation such as financial transactions.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: September 11, 2007
    Assignees: Georgia Tech Research Corporation, Infineon Technologies AG
    Inventors: Santosh Pande, Tao Zhang, Andre Dos Santos, Franz Josef Bruecklmayr
  • Electronic device with cavity and a method for producing the same
    Patent number: 7268436
    Abstract: An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by a cavity frame made of plastic and can have a cavity cover made of semiconductor material.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Robert Aigner, Albert Auburger, Frank Daeche, Guenter Ehrler, Andreas Meckes, Horst Theuss, Michael Weber
  • Method for fabricating a semiconductor having a field zone
    Patent number: 7268079
    Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Elmar Falck, Franz-Josef Niedernostheide, Hans-Joachim Schulze, Reiner Barthelmess
  • Generating a sampling clock signal in a communication block of a memory device
    Patent number: 7269093
    Abstract: A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Peter Gregorius, Martin Streibl
  • Method for printing contacts on a substrate
    Patent number: 7268080
    Abstract: A method for printing contacts utilizes photolithographic pattern reversal. A negative of the contact is printed on a resist layer. Unexposed portions of the resist layer are stripped to expose a first layer. The first layer is etched to remove exposed portions of the first layer not covered by the negative of the contact and to expose a second layer. A pattern reversal is performed to cure exposed portions of the second layer not covered by the first layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventor: Uwe Paul Schroeder
  • Memory cell with trench capacitor and vertical select transistor and an annular contact-making region formed between them
    Patent number: 7268381
    Abstract: The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Matthias Goldbach, Till Schlösser
  • Method for fabricating microchips using metal oxide masks
    Patent number: 7268037
    Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies, AG
    Inventors: Stefan Jakschik, Thomas Hecht, Uwe Schröder, Matthias Goldbach