Abstract: An optocoupler, for converting optical signals into electrical signals and vice versa, includes a package with a jack connector for receiving an optical waveguide. On a lower side of the package, surface-mountable outer contacts are arranged on an interconnection film. A mounting position for semiconductor chips, including one optical semiconductor chip and one application-specific semiconductor chip, is provided in the package on the optical axis of the optical waveguide. The optical semiconductor chip is aligned with the optical axis inside the package. The outer contacts are arranged outside the package on the flexible interconnection film. Between the mounting position and the outer contacts, the interconnection film includes a curved region which is embedded in the package material such that the surface-mountable outer contacts on the lower side of the package are freely accessible.

Abstract: A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface is suggested, wherein the memory area is adapted to be written by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: An integrated circuit having a multilayer capacitance arrangement and a method for producing an integrated circuit having a multilayer capacitance arrangement are disclosed.

Abstract: A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If so, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.

Abstract: The present invention provides a method for cleaning semiconductor devices through heterogeneous nucleation of cavitation bubbles. Heterogeneous nucleation is performed by applying sonic energy to a cleaning solution and a phase material in order to remove unwanted particles from semiconductor devices. A surfactant may be added to the phase material and the cleaning solution.

Abstract: A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a drain line, which is connected to a first supply voltage potential via a connecting resistor. The gate terminal is connected to a node of a gate line, onto which an input signal is coupled. The source terminal is coupled to a second supply voltage potential via a first resistor. The traveling wave amplifier also comprises at least one second normally off MOS transistor. In addition, the traveling wave amplifier further comprises a normally off bias MOS transistor. The normally off bias MOS transistor forms a current mirror with at least one of the second normally off MOS transistors. An output signal of the traveling wave amplifier is tapped off on the drain line.

Abstract: A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

Abstract: Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO2) substrate in capacitor structures of memory devices.

Abstract: A solderable device includes a substrate and a soldering pad overlying the substrate. A solder mask overlies the substrate and portions of the soldering pad. The solder mask has an opening that exposes a portion of the soldering pad. The opening has at least two edges that symmetrically overlie portions of the soldering pad.

Abstract: An electronic component includes at least two vertical semiconductor power devices and an electrically conductive contact clip. Each vertical semiconductor device has a first side with at least one first lead electrode and a second side opposing the first side with at least one second load electrode. The contact clip comprises a flat web portion and at least one peripheral rim portion extending from an edge region of the flat web portion. Each of the at least two vertical semiconductor power devices is attached, and electrically connected to, the lower surface of the flat web portion of the contact clip.

Abstract: The present invention relates to a method for determining an edge profile of a volume of a photoresist after a development process. At first, the volume of the photoresist is divided into cells. A chemical master equation is set up which reflects the stochastic kinetics of chemical reactions proceeding in cells of the volume of the photoresist during the development process. The chemical master equation is solved for a given development time on the basis of a Gillespie algorithm in order to determine developed and non-developed cells of the volume of the photoresist at the end of the development process. Finally, the edge profile of the volume of the photoresist after the development process is determined on the basis of a cluster of non-developed cells.

Abstract: A process produces metallic interconnects and contact surfaces on electronic components using a copper-nickel-gold layer structure. The copper core of the interconnects and contact surfaces is deposited by electroplating by means of a first resist mask made from positive resist. The copper core of the interconnects and contact surfaces is surrounded by a nickel-gold layer by means of a second resist mask. The interconnects and contact surfaces are produced by means of two resist masks arranged one on top of the other, in such a way that the copper which forms the core of the interconnect is completely surrounded by the nickel-gold layer, which extends above the copper core, and an adjoining layer that extends beneath the copper core and comprises a diffusion barrier and seed layer.

Abstract: For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.

Abstract: The method of the present invention relates to a method for producing a chip stack comprising the steps of manufacturing at least a first and a second integrated structure on a single substrate, an area of the first integrated structure and an area of the second integrated structure adjoining a respective first and second kerf area; providing a first redistribution layer on the first integrated structure on the substrate, said first redistribution layer at least partially extending beyond the area of the first integrated structure into the first kerf area, thereby forming a first integrated device area, wherein a first contact pad is arranged on the first redistribution layer in a first contacting area overlapping the first kerf area; providing a second redistribution layer on a second integrated structure on the substrate, including a second contact pad, thereby forming a second integrated device area; separating the first and second integrated device areas along a separation line defined by at least one of

Abstract: A method for structural analysis and correction of a system of differential equations described by a computer language is disclosed. A description of a physical system (in the form of equations, in particular differential equations) as a computer program in a computer system is included. Suitable bipartite graphs for examining the solubility of the equations are generated with the method. Erroneous descriptions can be determined and can possibly be corrected with the bipartite graphs. A computer system containing a computer-readable medium having computer-executable instructions for performing the method, and a corresponding data carrier are disclosed.

Abstract: An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

Abstract: A magnetoresistive memory cell includes N magnetoresistive elements conductively connected in series (where N is an integer greater than or equal to two). The magnetoresistive elements, respectively, are positioned between at least two adjacent conductive lines. At least one of the conductive lines is a partially split conductive line having at least one slit portion encompassing an interconnect running therethrough and connected to at least one adjacent magnetoresistive element.

Abstract: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.