Abstract: A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: Split cascode circuits include multiple cascode paths coupled between voltage supply rails. Each cascode path includes a pair of controllable switches. A feedback path is provided for at least one of the cascode circuit paths. An active load circuit may also have a split cascode structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascode circuits.

Abstract: The present application discloses a Transverse Electric (TE) polarizer. The TE polarizer includes a silicon-on-insulator substrate having a silicon dioxide layer. The TE polarizer further includes a waveguide embedded in the silicon dioxide layer. Additionally, the TE polarizer includes a plate structure embedded in the silicon dioxide layer substantially in parallel to the waveguide with a gap distance. In an embodiment, the plate structure induces an extra transmission loss to a Transverse Magnetic (TM) mode in a light wave traveling through the waveguide.

Abstract: A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.

Abstract: A photonic transceiver apparatus in QSFP package. The apparatus includes a case having a base member, two partial side members, and a lid member to provide a spatial volume with an opening at a back end of the base member. Additionally, the apparatus includes a PCB, installed inside the spatial volume over the base member having a pluggable electrical connector at the back end. Further, the apparatus includes multiple optical transmitting devices in mini-transmit-optical-sub-assembly package, each being mounted on a common support structure and having a laser output port in reversed orientation toward the back end. Furthermore, the apparatus includes a silicon photonics chip, including a fiber-to-silicon attachment module, mounted on the PCB and coupled to a modulation driver module and a trans-impedance amplifier module. Moreover, the apparatus includes a pair of optical input/output ports being back connected to the fiber-to-silicon attachment module.

Abstract: An apparatus of polarization self-compensated delay line interferometer. The apparatus includes a first waveguide arm of a first material of a first length disposed between an input coupler and an output coupler and a second waveguide arm of the first material of a second length different from the first length disposed between the same input coupler and the same output coupler. The apparatus produces an interference spectrum with multiple periodic passband peaks where certain TE (transverse electric) and TM (transverse magnetic) polarization mode passband peaks are lined up. The apparatus further includes a section of waveguide of a birefringence material of a third length added to the second waveguide arm to induce a phase shift of the lined-up TE/TM passband peaks to a designated grid as corresponding polarization compensated channels of a wide optical band.

Abstract: The present disclosure provides an optical equalizer for photonics system in an electric-optical communication network. The optical equalizer includes an input port and an output port. Additionally, the optical equalizer includes a filter having a number of stages coupled to each other in a multi-stage series with an output terminal of any stage being coupled to an input terminal of an adjacent next stage while the input terminal of a first stage of the multi-stage series being coupled from the input port. Each stage includes a tap terminal configured to pass an optical power factored by a coefficient of multiplication from the corresponding input terminal of the stage to a tap-output path characterized by a corresponding phase delay. Furthermore, the optical equalizer includes a combiner configured to sum up the optical powers respectively from the number of tap-output paths of the multi-stage series to the output port.

Abstract: The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: The present invention is directed to data communication. In a specific embodiment, a known data segment is received through a data communication link. The received data is equalized by an equalizer using an adjustable equalization parameter. The output of the equalizer is sampled, and a waveform is obtained by sweeping one or more sampler parameters. The waveform is evaluated by comparing it to the known data segment. Based on the quality of the waveform, equalizer parameter is determined. There are other embodiments as well.

Abstract: The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.

Abstract: An integrated photo detector with enhanced electrostatic discharge damage (ESD) protection. The integrated photo detector includes a first photodiode formed in the SOI substrate and associated with a first p-electrode and a first n-electrode. Additionally, the integrated photo detector includes a second photodiode formed in the SOI substrate associated with a second p-electrode and a second n-electrode forming a capacitance no larger than a few femto Faradays. Moreover, the integrated photo detector includes a first electrode and a second electrode disposed respectively on the SOI substrate. The first/second electrode is respectively connected to the first p/n-electrode via a first/second metallic layer patterned with a reduced width from the first/second electrode to the first p/n-electrode and connected to the second p/n-electrode via a first/second metallic wire to make a parallel coupling between the first photodiode and the second photodiode with an ESD threshold of about 100V.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

Abstract: Systems and methods described herein include methods and systems for controlling bias voltage provided to an optical modulating device. The optical modulating device is biased at a bias point that is different from a null point of the device such that an offset to the received optical power due to limited extinction ratio is reduced.

Abstract: A method of operating a computer network system configured with disaggregated inputs/outputs. This system can be configured in a leaf-spine architecture and include a router coupled to a network source, a plurality of core switches coupled to the router, a plurality of aggregator switches coupled to each of the plurality of core switches, and a plurality of rack modules coupled to each of the plurality of aggregator switches. Each of rack modules can include an I/O appliance with a downstream aggregator module, a plurality of server devices each with PCIe interfaces, and an upstream aggregator module that aggregates each of the PCIe interfaces. A high-speed link can be configured between the downstream and upstream aggregator modules via aggregation of many serial lanes to provide reliable high speed bit stream transport over long distances, which allows for better utilization of resources and scalability of memory capacity independent of the server count.