Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.

Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a line driver with transistors directly coupled to the ground, and a bias voltage is coupled common mode resistors of the line driver. There are other embodiments as well.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: An apparatus for modulating a beam of light with balanced push-pull mechanism. The apparatus includes a first waveguide comprising a first PN junction on a substrate and a second waveguide comprising a second PN junction on the silicon-on-insulator substrate. The second PN junction is a replica of the first PN junction shifted with a distance. The apparatus further includes a first source electrode and a first ground electrode coupled respectively with the first PN junction and a second source electrode and a second ground electrode coupled respectively with the second PN junction. The apparatus additionally includes a third ground electrode disposed near the second PN junction at the distance away from the second ground electrode, wherein the first ground electrode, the second ground electrode, and the third ground electrode are commonly grounded to have both PN junctions subjected to a substantially same electric field varied in ground-source-ground pattern.

Abstract: The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.

Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

Abstract: A transimpedance amplifier (TIA) device and method of operation therefor. The TIA device can include a semiconductor substrate, a TIA with an input and output configured on the semiconductor substrate, and an overload buffer module coupled to the input terminal of the TIA. The overload buffer module can include a variable current source having an input and an output, and a biased buffer diode coupled to the output of the variable current source and to a ground node. The method of operation can include replicating, by the overload buffer module, the current-voltage (I/V) characteristics of the DC input signal at the output of the overload buffer module, wherein the overload buffer module reduces a total harmonic distortion (THD) of a DC output signal from the output of the TIA.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. More specifically, embodiments of the present invention provide an off-quadrature modulation system. Once an off-quadrature modulation position is determined, a ratio between DC power transfer amplitude and dither tone amplitude for a modulator is as a control loop target to stabilize off-quadrature modulation. DC power transfer amplitude is obtained by measuring and sampling the output of an optical modulator. Dither tone amplitude is obtained by measuring and sampling the modulator output and performing calculation using the optical modulator output values and corresponding dither tone values. There are other embodiments as well.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

Abstract: A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Abstract: Apparatus and method for compensating for transmitter errors in an optical communication system are provided. In certain configurations herein, a receiver is provided for processing an analog signal vector representing an optical signal received from a transmitter. The receiver includes an analog front-end that converts the analog signal vector into a digital signal vector including a digital representation of an I component and a Q component of the optical signal. The receiver further includes a digital signal processing circuit configured to process the digital signal vector to recover data, and the digital signal processing circuit includes a transmitter error compensation system that compensates the digital signal vector for at least one of a transmit skew error of the transmitter or a modulator biasing error of the transmitter.

Abstract: The present invention is directed to optical communication systems and methods thereof. In various embodiments, the present invention provides method for linearizing Mach Zehnder modulators by digital pre-compensation and adjusting the gain of the driver and/or the modulation index. The pre-compensation can be implemented as a digital pre-compensation algorithm, which is a part of an adaptive feedback loop. There are other embodiments as well.

Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Abstract: A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, embodiments of the present invention provide a differential amplifier that has a differential amplifier section, a current source, and a feedback section. The differential amplifier section comprises NMOS transistors that receives two voltage inputs and generate a differential output. The current source provides a long tail for the differential amplifier section. The feedback section generates a feedback voltage based on a reference bias voltage. The feedback voltage is used by an amplifier to control the current source and to keep the biasing and gain of the differential amplifier substantially constant. There are other embodiments as well.

Abstract: A waveguide-based polarization splitter-rotator (PSR) includes a converter with tapered rib-structure configured to convert TM0/TE0 polarization mode of an input light to a TE1/TE0 mode, a splitter coupled to the first plane for splitting the input light evenly to a first wave at a first port and a second wave at a second port. Furthermore, the PSR includes a phase shifter having a first arm coupled to first port and a second arm coupled to the second port. The first arm guides the first wave to a third port with no phase shift while the second arm adds 90 or 270 degrees to the second wave. The PSR also includes a 2×2 MMI coupler for coupling the first wave and the second wave to output a first output light in TE0 mode exclusively from TM0 mode and a second output light in TE0 mode exclusively from TE0 mode.

Abstract: A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.