Abstract: A wireless power transmitter comprises a bridge inverter configured to receive a DC power signal and generate an AC power signal according to an operating frequency, a resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto, and control logic configured to cause the resonant tank to reconfigure and adjust its resonant frequency for a particular receiver type of a wireless power receiver with which a mutual inductance relationship is desired. A method comprises determining a receiver type for a wireless power receiver with which it is desired to establish a mutual inductance relationship for wireless power transfer, and generating a wireless power signal with a wireless power transmitter having an operating frequency and resonant tank that is adjusted for a particular receiver type.

Abstract: A wireless power transmitter comprises a bridge inverter including a first switch and a second switch coupled together with a first switching node therebetween, and a first capacitor coupled to the first switching node. The transmitter further includes control logic configured to control the first switch and the second switch according to an operating frequency to generate an AC power signal from a DC power signal, and a resonant tank operably coupled to the first switching node of the bridge inverter, the resonant tank configured to receive the AC power signal and generate an electromagnetic field responsive thereto. A method for operating the wireless power transmitter and a method for making the wireless power transmitter are also disclosed.

Abstract: A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.

Abstract: A switch queue predictive protocol (SQPP) includes a packet switching system including: a switch fabric having a cross-point switch, and a plurality of line cards, each coupled to the switch fabric. A cross-point buffer is located at each cross-point of the cross-point switch. The switch fabric also includes a plurality of actual available queue space tables (AAQSTs), each identifying the actual queue space available in a row of the cross-point buffers. Each of the line cards includes an input buffer, an output buffer, and a predicted available queue space table (PAQST) identifying predicted queue space available in a corresponding row of the cross-point buffers. Packet information is transmitted from a source line card to the switch fabric only if available queue space is predicted by the corresponding PAQST. The switch fabric uses the AAQST to update the PAQST after packet information is transmitted to a destination line card.

Abstract: In accordance with this invention, integrated circuits are manufactured using parallel processing to manufacture separately selected parts of finished integrated circuits. Upon completion of the parts, the parts are joined together to form the completed integrated circuit. For example, a semiconductor wafer containing active and passive semiconductor regions is fabricated through the first layer of insulation and first conductive contacts. Separately, an interconnect structure is fabricated on a separate fabrication line to include all the layers of interconnects required to form a completed integrated circuit when joined to the wafer. The interconnect structure is joined to the wafer to form the complete integrated device. The interconnect structure can be fabricated to exclude from the integrated circuit those portions of the wafer which have been determined by test to be defective.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.

Abstract: In accordance with the present invention, an improved output driver stage for a BiCMOS logic gate is provided by including a clamping transistor. Such clamping transistor avoids, in the pull-up bipolar transistor, both degradation of current gain and emitter-to-collector breakdown.