Abstract: A wireless status indicator for a wireless power transfer system includes an object configured to wirelessly generate power responsive to a magnetic flux field of a wireless power transmitter and to generate a status indication of the wireless power transfer system. A wireless power transfer system comprises a wireless power status indicator configured to wirelessly generate power responsive to a wireless power signal and to generate a status indication of the wireless power transfer system. A related method includes generating power by a wireless status indicator and generating a status indication responsive to a wireless power signal. The wireless status indicator is a separate stand-alone device than a wireless power transmitter and wireless power receiver involved in the wireless power transfer. The status indication corresponds to a state of wireless power transfer.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: An apparatus comprises a phased array antenna panel, a plurality of amplifier circuits, and a plurality of beamformer circuits. The phased array antenna panel generally comprises a plurality of antenna elements. Each of the amplifier circuits is mounted on the phased array antenna panel adjacent to a respective one of the plurality of antenna elements and each of the amplifier circuits has one or more first ports directly coupled to the respective antenna element. Each of the beamformer circuits is mounted on the phased array antenna panel adjacent to a number of the amplifier circuits. Each of the beamformer circuits has one or more second ports directly coupled to each of the adjacent amplifier circuits. Each of the beamformer circuits is generally configured to exchange a plurality of radio-frequency signals with each of the adjacent amplifier circuits via the second ports.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a variable current and (ii) a constant current. The variable current may be proportional to a temperature of the first circuit. The second circuit may be configured to present a resistance through a plurality of first transistors between two ports in response to both the variable current and the constant current. The resistance may have a predefined dependence on the temperature.

Abstract: A method of adaptively operating a transmit detection circuit is presented. The method includes powering the transmit detection circuit with a capacitor charged by an LDO; receiving a digital ping signal from a transmitter; receiving a clock signal from a local oscillator; updating a register to accommodate timing of the digital ping signal; and generating a signal indicating whether the transmitter is present.

Abstract: In accordance with embodiments of the present invention, data is modulated for transmission phase modulation. A method of transmitting data in a wireless power transmitter, includes transmitting a wireless power signal; encoding data to be transmitted into symbols; determining a phase shift to represent the symbols; and phase modulating the wireless power signal with the phase shift. A method of receiving data in a wireless power receiver includes receiving a wireless power signal that includes a phase modulated data signal; determining a period of each cycle of the wireless power signal; providing a running average over N?1 cycles of the wireless power signal, where N represents the number of cycles of the wireless power signal in which each phase modulation is provided; and decoding the data from the running average.

Abstract: According to another embodiment, a system includes a driver circuit that drives a first output and a second output; a coil coupled between the first output and the second output such that the driver circuit drives current through the coil in response to control signals; and a programmable slew circuit coupled to the driver circuit. In some embodiments, a switch is coupled between the first output and the coil. In some embodiments an over-voltage protection circuit is coupled to protect the driver circuit.

Abstract: In some embodiments, a coil design system is provided. In particular, a method of providing an optimized position locating sensor coil design in presented. The method includes receiving a coil design; simulating position determination with the coil design to form a simulated performance; comparing the simulated response with the specification to provide a comparison; and modifying the coil design based on a comparison between the simulated performance and a performance specification to arrive at an updated coil design.

Abstract: An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

Abstract: An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.

Abstract: A method of implementing a radio frequency (RF) switch comprises the steps of forming a first switch device on an integrated circuit substrate, forming a second switch device on the integrated circuit substrate, connecting the first switch device between a first pad and a second pad of the integrated circuit, connecting the second switch device between the second pad and a third pad of the integrated circuit, directly connecting a first control pad of the integrated circuit for receiving a first digital control signal to a control terminal of the first switch device, and directly connecting a second control pad of the integrated circuit for receiving a second digital control signal to a control terminal of the second switch device. A threshold voltage of the first and second switch devices is generally modified to allow being directly driven by the first digital control signal or the second digital control signal.

Abstract: A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit.

Abstract: An apparatus includes one or more field effect transistors configured as a switch. Each of the one or more field effect transistors comprises one or more source diffusions, one or more drain diffusions, and one or more gate fingers. Each of the one or more gate fingers is disposed between a source diffusion and a drain diffusion. A first electrical connection to the one or more source diffusions is made using one or more source electrodes that extend from a first end for a first length along a long axis of the source diffusions. A second electrical connection to the one or more drain diffusions is made using one or more drain electrodes that extend from a second end for a second length along a long axis of the drain diffusions. The first length of the one or more source electrodes and the second length of the one or more drain electrodes are generally selected to avoid juxtaposition of the one or more source electrodes and the one or more drain electrodes.

Abstract: An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

Abstract: An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate signal may be differential. The slicer may be configured to generate an output signal by slicing the second intermediate signal. The output signal may be single-ended.

Abstract: An apparatus comprising an accumulator circuit and an offset register. The accumulator circuit may be configured to (a) receive a plurality of frequency offset values from a plurality of sourcing DPLLs and (b) generate a current combined offset value in response to a sum of the frequency offset values. The offset register may be configured to (a) store an offset value corresponding to the current combined offset value in a first mode and (b) store an offset value corresponding to an updated offset value in a second mode. The updated offset value may comprise a difference between the offset value stored in the offset register and the current combined offset value. The offset value may be presented to a receiving DPLL during a re-arrangement of the sourcing DPLLs. Presenting the offset value may reduce a phase transient caused by the re-arrangement.

Abstract: An apparatus includes an amplifier and a gain control circuit. The amplifier may be configured to provide multiple gain steps. The gain control circuit may be configured to provide fast and precise changes between the multiple gain steps of the amplifier. The gain control circuit may be further configured to change an impedance of the amplifier to switch between the gain steps. The gain control circuit may be further configured to compensate for changes in frequency response related to changing the impedance. The gain control circuit may be further configured to inject a complementary charge to an input of the amplifier to correct a bias voltage deviation and a transient caused by the gain control circuit.

Abstract: An apparatus includes a first continuous time linear equalizer circuit and a second continuous time linear equalizer circuit. The first continuous time linear equalizer circuit may be configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor. The second continuous time linear equalizer circuit may be configured to generate an output signal by filtering the intermediate signal.

Abstract: An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.

Abstract: A power converter control circuit includes a first ramp generator connected to an input voltage and configured to produce a first ramp signal; a second ramp generator connected to the input voltage and configured to produce a second ramp signal; an error amplifier configured to produce an error amplifier output. The first ramp signal and the error amplifier output are used to produce a first (pulse width modulation) PWM signal and the second ramp signal and the error amplifier output are used to produce a second PWM signal. The first and second PWM signals control an operating state of the circuit. In some embodiments, the first ramp signal includes an extended ramp reset time. In some embodiments, the first ramp generator includes a switching device, a current source, and a capacitor.