Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.
Abstract: A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, provides an index value and activates a hit signal if the hashed output value matches an entry of the CAM. A random access memory (RAM) receives the index value from the CAM. The RAM stores a collision resolution value and information associated with the character string in an entry associated with the index value. The RAM provides this information and collision resolution value in response to the index value. Logic circuitry indicates a collision if the hit signal is activated and the collision resolution value provided by the hardware hashing circuit does not match the collision resolution value provided by the RAM.
Abstract: A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.
Abstract: A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which prevents pull-up and pull-down devices (which drive the output signal), from turning on at the same time.
Abstract: Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.
Abstract: An auto-adaptive digital phase locked loop (DPLL) includes a phase detector comprising an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock. The DPLL also includes a programmable first counter that counts down at the generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output that outputs a counter state based on the generated clock and the integer value M. A first register has a first input that receives the reference event, a second input that receives the counter state, and an output that outputs a sample value N(t), wherein the register stores the counter state as the sampled value N(t) that represents a code for a phase between the reference event and the counter state.
Abstract: A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have the same predetermined value. The activated reset control signal asynchronously resets a pair of series connected flip-flops. The deactivated reset control signal enables the flip-flops to synchronously propagate a fixed logic signal in response to a clock signal of a complementary input clock signal pair. The output signal of the series-connected flip-flops is used to select the data output clock signal from the first complementary clock signal pair and the second complementary clock signal pair.
Abstract: A method and apparatus for burn-in of semiconductor devices is disclosed. A semiconductor device that includes built-in self test circuitry is coupled to a socket on a burn-in board. The burn in board and the semiconductor device are heated. Burn-in instructions can be transmitted to the semiconductor device through a JTAG terminal of the semiconductor device. Upon receiving a burn-in instruction through a JTAG terminal, the built-in self test circuitry is operable to perform one or more burn-in function. This allows for burn-in of a semiconductor device without any transfer of data through the data input terminals of the semiconductor device.
Type:
Grant
Filed:
October 10, 2003
Date of Patent:
September 25, 2007
Assignee:
Integrated Device Technology, Inc.
Inventors:
Moussa Sobaiti, Robert Shrank, Sudhakar Reddy, Yousif Jirjis
Abstract: A frequency synthesizer IC is disclosed that includes a variable delay circuit, a fractional-N phase locked loop circuit, and a feedback loop. The variable delay circuit is electrically coupled to the input of the fractional-N phase locked loop circuit. The feedback loop couples a first control signal from the fractional-N phase locked loop to the variable delay circuit. The variable delay circuit generates a reference signal that has a phase delay that varies in accordance with a second control signal and a first control signal. The fractional-N phase locked loop circuit is operable upon receiving the reference signal to generate the first control signal, the second control signal, and an output signal having a frequency that is a non-integer product of the reference signal.
Abstract: A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The feedback signals are then received and compared. Based on the comparisons, the skew between the output signals is adjusted.
Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M?(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
Abstract: Time-slot interchange (TSI) switches include a data memory having first entries therein that contain serial data received by the switch and a connection memory having second entries therein. When programmed, these second entries contain addresses of a plurality of the first entries in the data memory and switching modes that have been assigned to the plurality of the first entries. A control circuit is also provided to automatically program a block of the second entries in the connection memory with updated switching modes during an efficient burst program mode of operation. An internal bypass feature is also provided to support efficient testing/debugging of downstream devices in a communications path.
Type:
Grant
Filed:
December 6, 2002
Date of Patent:
September 4, 2007
Assignee:
Integrated Device Technology, Inc.
Inventors:
Alexander P. Goldhammer, Angus David Starr MacAdam
Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.
Type:
Grant
Filed:
November 26, 2001
Date of Patent:
August 28, 2007
Assignee:
Integrated Device Technology, Inc.
Inventors:
Matthew D. Ornes, Christopher I. W. Norrie, Gene K. Chui, Onchuen (Daryn) Lau
Abstract: Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.
Type:
Grant
Filed:
December 20, 2002
Date of Patent:
August 21, 2007
Assignee:
Integrated Device Technology, Inc.
Inventors:
Alexander P. Goldhammer, Angus David Starr MacAdam, Frank Matthews
Abstract: CAM-based search engines may be configured to support multiple databases within a CAM core. These databases may represent tables for different applications, which can be searched sequentially in response to a single indirect instruction that is loaded during a control cycle. The databases to be searched may be identified by a multi-database search instruction that is loaded during a single data cycle, which may overlap with the control cycle. In some cases, the databases may be searched using variations of a primary search key, so that it is unnecessary to repeatedly load the entire search key across a network interface for each search operation within a respective database. Instead, shorter replacement key segments may be loaded for each of a plurality of the search operations and these replacement key segments may be combined with one or more segments of the primary search key in the CAM core to define a desired search key for a respective search operation.
Type:
Grant
Filed:
September 18, 2006
Date of Patent:
August 21, 2007
Assignee:
Integrated Device Technology, Inc.
Inventors:
Harmeet Bhugra, Kenneth Branth, John R. Mick, Jr., Jakob Saxtorph
Abstract: An auto voltage sense circuit uses voltage controlled current sources to generate a desired reference voltage level that closely tracks the variations and changes of a first voltage level and a second voltage level. The auto voltage sensing circuit includes a first voltage controlled current source operable to receive the first voltage level to generate a reference current that is proportional to the first voltage level. The auto voltage sensing circuit also includes a second voltage controlled current source operable to receive the second voltage level and the reference voltage to generate an output current that is proportional to the difference between the second voltage level and the reference voltage. The reference voltage causes the output current to be approximately equal to the reference current so as to generate a reference voltage that is proportional to the difference between the second voltage level and the first voltage level.
Abstract: A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.
Abstract: Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.
Abstract: FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through the FIFO memory device. In particular, the diagnostic bits identify all cases of whether the data word includes a corrected or uncorrected error, is without error or is unchecked for errors because the data word did not pass through error detection and correction circuitry within the FIFO memory device.