Abstract: A dual-port Static Random Access Memory (SRAM) cell is disclosed that includes a storage element that is operable to store a data bit and a complement data bit. The dual-port SRAM cell further includes read access circuitry dedicated exclusively to a read operation and write access circuitry dedicated exclusively to a write operation. The read operation and the write operation are performed in a staggered manner. With the read operation performed exclusive on one port and the write operation performed exclusively on the other port of the SRAM cell, smaller transistors can be used to reduce the size of the SRAM cell.

Abstract: Content addressable memory (CAM) devices have CAM cells therein that are electrically coupled to a NAND-type compare circuit. This NAND-type compare circuit is responsive to a first operand (K) containing true and complementary bits of an applied search key and a second operand (D) containing true and complementary bits of a stored search word. The NAND-type compare circuit includes a first string of transistors connected end-to-end in series from a first terminal to a second terminal and a second string of transistors connected end-to-end in series from the first terminal to the second terminal. This first string of transistors has gate terminals responsive to the first operand and the second string of transistors has gate terminals responsive to the second operand.

Abstract: A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can be linked by per-entry counters associated with each string, or by a state machine. The strings in the CAM array are compared with a packet, which is shifted one symbol at a time (because the strings can start on any boundary). When the CAM detects a match, the CAM skips over the string that resulted in the match, thereby preventing erroneous matches. The CAM allows parallel matching to be performed for multiple rules. If the contents of a packet match all of the strings of a rule, in order, then the CME asserts a match/index signal that identifies the matched rule.

Abstract: Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.

Abstract: A deficit round-robin scheduler including a round-robin table configured to store a plurality of cycle link lists, wherein each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries, wherein each of the flow table entries is associated with a corresponding flow, and therefore has a corresponding FLID value. A packet queue is associated with each flow table entry, wherein each packet queue is capable of storing a plurality of packets. The deficit round-robin scheduler also included an idle cycle register having an idle cycle entry corresponding with each of the cycle link lists, wherein each idle cycle entry identifies the corresponding cycle link list as active or idle.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: The application discloses driver circuits including a current source, a current sink, and a current steering circuit configured to provide current to a load. The current sink is configured to be controlled according to a regulated voltage. Signal generator circuits are also disclosed.

Abstract: A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows for more. In a supplemental or alternate embodiment, at least one virtual bus is limited to having no devices on it. A non-transparent bridge is provided on at least one of the special buses for providing cross-border routing of packets from one root domain to another root domain. The number-of-devices limitation placed on the special bus reduces the number of bits needed in a corresponding Device identifying field of a destination ID Tag to 4 or less, this integer number being smaller than the prescribed 5 bits called for by the PCI-Express standard for addressing the maximum of 32 devices per bus.

Abstract: A package for a flip-chip integrated circuit device and a packaged flip-chip integrated circuit device that include ground strips and power strips disposed on the top surface of the package substrate. Decoupling capacitors are disposed over and electrically coupled to a ground strip and are disposed over and electrically coupled to a power strip. Microvias electrically couple the power strips to a power plane and electrically couple the ground strip to a ground plane. Each power strip and ground strip extend within a die attach region of the package substrate such that a semiconductor die can be bonded thereto for coupling power and ground between the semiconductor die and the decoupling capacitors. The power strip and ground strip provide low impedance pathways between the flip-chip semiconductor die and the decoupling capacitors. Thereby, effective decoupling capacitance is provided that is suitable for high frequency applications.

Abstract: In one application, a method according to an embodiment of the invention is used to enable a display of proportionally spaced characters using a fixed-font display controller.

Abstract: A data transmitter pre-emphasizes the amplitude and frequency bandwidth of a data signal. A data tap generator delays the data signal to generate multiple data tap signals, each of which is delayed by an integer multiple of a data period. A delay module further delays one of the data tap signals by a delay time that is less than the data period to generate a delayed data signal. The delay time of the delayed data signal determines a frequency bandwidth pre-emphasis for the data signal. A filter module multiplies the amplitudes of the data tap signals and the delayed data signal by coefficients to generate signal components of a pre-emphasized data signal. The coefficients of the filter module determine the amplitude pre-emphasis for the data signal. The filter module sums the signal components to generate the pre-emphasized data signal, which includes both the frequency bandwidth pre-emphasis and the amplitude pre-emphasis.

Abstract: An over-voltage tolerant input stage in a semiconductor device is disclosed. The input stage includes: an input pad for receiving an input signal to the semiconductor device, a buffer coupled to the input pad for buffering the input signal, a pullup circuit for limiting current in the input signal, a switching circuit coupled to the input pad for controlling the pullup circuit, and a voltage supply coupled to the input pad, the pullup circuit and the switching circuit. In operation, the switching circuit is enabled to cause the pullup circuit to stop current flow between the input signal and voltage supply in the event of an over-voltage condition.

Abstract: A method and apparatus for Clock and PLL N-Divider Switch have been disclosed.

Abstract: Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in self repair (BISR) of hard memory defects and/or compare logic defects in the plurality of CAM array blocks concurrently with operations to search entries in the plurality of CAM array blocks.

Abstract: A computer audio system includes an audio codec and a tone controller. The audio codec is operably coupled to receive audio information, which includes tone control settings, PCM digital audio inputs and PCM digital audio outputs. In addition, the audio codec may receive audio information as analog input signals via a line-in, a CD input, or an auxiliary input. Based on the audio information, the audio codec provides a first stereo output, a second stereo output and a monotone audio output. The tone controller is operably coupled to the audio codec and includes a low pass filter, a high pass filter, a band pass filter, and a summing module. The low pass filter is operably coupled to filter the monotone audio output and isolates bass components of the audio signal being processed. By further coupling a volume control module to the low pass filter, the bass component of the audio signal being processed may be varied.

Abstract: Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected one of a plurality of CAM arrays to the plurality of global word lines in response to detecting a match in the selected one of the plurality of CAM arrays.

Abstract: A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where “n” is a positive integer greater than one.

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom and a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal. The PLL further includes a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current. The current-mode loop filter circuit may be self-biased. For example, the current-mode loop filter circuit and the charge pump may be biased responsive to a common bias control signal generated by the current-mode loop filter circuit.

Abstract: A buffer bypass circuit for reducing latency in information transfers to a bus is described. Access to the bus is governed by a bus arbiter employing a bus parking scheme. The buffer bypass circuit comprises a multiplexer and logic configured such that the information to be transferred is either buffered in a buffer if a grant generated by the bus arbiter indicates that the bus is unavailable, or transferred directly to the bus if the grant indicates that the bus is available and the buffer is empty at the time.