Abstract: A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.

Abstract: A non-destructive method of identifying a type of compound in a sample using an acoustic microscope, particularly, identifying the type of compound used in an integrated circuit package by comparing attributes of the tested molding compound with known attributes of known compounds to identify the compound being evaluated. The attributes that are compared include voltage, attenuation, peak frequency, average frequency, and the velocity of reflected sound.

Abstract: A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated.

Abstract: A substrate has defined therein one or more active regions. A layer of polysilicon is deposited and patterned to form gates for various CMOS devices. A masking layer is then deposited and selectively etched to leave exposed portions of the substrate. Dopants of a first conductivity type are implanted into the exposed portions of the substrate to form one or more well regions of the first conductivity type. Using this masking layer and the polysilicon gates left exposed thereby as a mask, dopants of a second conductivity type are then implanted into the substrate to form source and drain regions of the second conductivity type in the well regions of the first conductivity type. The masking layer is then removed. In this manner, source and drain regions may be formed using the same masking layer used to define the well within which the source and drain regions lie, thereby reducing both time and expense in the fabrication of CMOS devices.

Abstract: A method, apparatus and computer program product for generating a texture map having a plurality of levels of detail for use in rendering an image which is displayed on a graphical display. A specified level of detail of the texture map is encoded as a sum of a plurality of scaled wavelet basis functions. A texture map corresponding to a more coarse level of detail of the texture map is generated from the wavelets comprising the lower frequency wavelets of the wavelet basis functions of the texture map corresponding to a finer level of detail. Preferably, the wavelet basis functions comprise Haar wavelet basis functions. Lower frequency wavelets from which the coarser level of detail texture map is reconstructed may comprise the lower half of the frequencies of the wavelet basis functions of the texture map corresponding to the immediately finer level of detail.

Abstract: An oscillator circuit includes biasing branches in the input section for permitting the oscillator gain and center frequency to be easily adjusted depending on design requirements. Accordingly, the oscillator circuit can be designed so as to have a lower overall gain and bandwidth yet operative at desired high frequencies. An output section includes a high-swing cascode current mirror for rejecting noise perturbations on the power supply so that they do not enter the oscillator stage, thus reducing jitter in the PLL frequency. The output section can be biased by a current mirror section so as to feed back an output voltage to one of the biasing branches of the input section, further lowering the overall gain and bandwidth of the oscillator circuit.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when the other ports are reading previously-stored data of opposite polarity. A parallel write capability is disclosed which eliminates such row contention by using the other ports of a multi-port memory to assist in writing the memory cell. By forcing the other ports into a write of the same data there can be no contention. Whenever a read port accesses the same row as a write port, the read port's bitline corresponding to the selected column for the write port is also forced into a write of the write port's data, along with the write port's bitline corresponding to the selected column of the write port. The read port's data is unaffected regardless of whether the selected column for the read port differs from the selected column for the write port.

Abstract: A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated and stored into a segment register much faster than if system validation checks were also performed. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and preferably does not react with either the reflective layer or the anti-reflective layer. In particular embodiments, the barrier layer is a thin layer of silicon dioxide SiO.sub.2 or silicon nitride Si.sub.3 N.sub.4, and the anti-reflective layer is titanium-tungsten TiW, titanium nitride TiN, or amorphous silicon.

Abstract: An antifuse redundancy circuit operates with transparency to external circuitry and users. In one embodiment, an antifuse redundancy circuit incorporates two antifuses rather than one. The circuit is arranged so that both antifuses may be simultaneously programmed and read. If a single antifuse is programmed without programming the other antifuse, the antifuse redundancy circuit will register a programmed antifuse. Additionally, if a single programmed antifuse is unintentionally deprogrammed after both antifuses in the redundancy circuit have been programmed, the antifuse redundancy circuit will continue to register a programmed antifuse. The result is both an increase in manufacturing yield and an increase in the reliability of integrated circuits utilizing antifuses.

Abstract: A method for improving the load time of code and data descriptors is provided. The invention utilizes hardware validation logic for code and data descriptors, but uses a software program to validate system descriptors. In those instances where the descriptor being loaded is a code or data descriptor, system validation checks are not performed. This allows code and data descriptors to be validated during the write back stage of the descriptor store operation, thereby eliminating processing delays typically associated with performing validation. If the descriptor is found invalid by the hardware validation logic, a branch is made to a software program which is used to determine whether the descriptor is invalid, or is actually a system descriptor. If it is a system descriptor, then system descriptor validation checks are performed by a software program.

Abstract: An apparatus and method for measuring parasitic differences between dissimilar conductive paths on a semiconductor is provided. The apparatus provides a ring oscillator which has two propagation paths. The first path is traversed on a logical transition from low to high, and the second path is traversed on a logical transition from high to low. The gate stages for the first path may be interconnected via a metal conductive layer, and the gate stages for the second path may be connected to a dissimilar metal, or polycide, for example. A single output signal is produced which has a period equal to twice the delay of the inverter stages, plus any delay associated with the parasitic difference in the two paths. The duty cycle of the periodic signal may then be used to determine the parasitic difference between the two materials used to interconnect the stages in the ring oscillator.

Abstract: An apparatus and method for improving the execution speed of particular micro instruction sequences is provided, and which allows for exception handling of the micro instruction sequences, as needed. During execution of a micro instruction sequence, particular registers are allowed to be overwritten prior to completion of the entire micro instruction sequence. A tracking mechanism is provided which tracks which registers are overwritten, and restoration logic is provided which stores the "old" contents of the particular registers. If the micro instruction sequence cannot complete, due to a fault, for example, the tracking mechanism indicates which registers have been overwritten, and the restoration logic provides the "old" values to be restored.

Abstract: An image generation system having a processing element array comprised of a plurality of processing elements interconnected so that processing elements may communicate with other processing elements in the processing element array. A linear expression evaluator provides coefficients of linear expressions which define object primitives to the processing element array and a processing element array controller provides instruction and control data. A central control unit controls the flow of data to and from the processing element array and controls the presentation of linear expression coefficients to the linear expression evaluator. Methods, apparatus and program products include assigning home pixel addresses corresponding to pixels of the screen regions to the plurality of processing elements. A database of geometric primitives is traversed and each primitive is assigned processing elements.

Abstract: Integrated circuit access times are reduced by an input structure in which input signals are routed through a low resistance path from the input pad directly to the interior of the integrated circuit without using an input driver.

Abstract: Two connectors located directly opposite each other on opposite sides of a printed circuit board are attached together and to the circuit board by means of keys integral to the connectors.

Abstract: An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag array tracking a page size portion of the data array. Indexing into each of the tag arrays is accomplished using the page index from either of the virtual address or the physical address. In addition, selection of indexed tags from the tag arrays is performed by array selection logic which utilizes portions of either of the virtual page number or the physical page number.