Abstract: A method for manufacturing a magnetic random access memory element having increased retention and low resistance area product (RA). A MgO layer is deposited to contact a magnetic free layer of the memory element. The MgO layer is deposited in a sputter deposition chamber using a DC power and a Mg target to deposit Mg. The deposition of Mg is periodically stopped and oxygen introduced into the deposition chamber. This process is repeated a desired number of times, resulting in a multi-layer structure. The resulting MgO layer provides excellent interfacial perpendicular magnetic anisotropy to the magnetic free layer while also having a low RA.

Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.

Abstract: A magnetic field transducer mounting apparatus can include a first mount configured to fixedly couple to a side surface of a wafer test fixture magnet, and a second and third mount configured to adjustably position a magnetic field transducer in a predetermined location proximate a face of the wafer test fixture magnet.

Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into a plurality of segments, wherein each segment of the cache memory is direct mapped to a corresponding segment of the memory bank, wherein an address of each of the second plurality of data words is mapped to a corresponding segment in the cache memory, and wherein data words from a particular segment of the memory bank only get stored in a corresponding direct mapped segment of the cache memory.

Abstract: A network device implements a repetition scheme to generate a repetition-encoded forward error correction (FEC) codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of N offset-shifted bit sequences. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. The set of N offset-shifted bit sequences are allocated into N orthogonal frequency-division multiplexing (OFDM) symbols, wherein each offset-shifted bit sequence is allocated over a corresponding OFDM symbol.

Abstract: A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.

Abstract: An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal. The output circuit includes an output driver circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit, when activated, generates the output signal indicative of the second power supply voltage in response to a modified pull-up signal being the pull-up signal level-shifted to a third voltage range. The pull-down circuit, when activated, generates the output signal being the ground potential in response to the pull-down signal.

Abstract: A network device implements a repetition scheme to generate a repetition-encoded FEC codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of bit sequences concatenated together. The set of bit sequences corresponds to a set of OFDM symbols. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. In one embodiment, a right cyclic shift is used to offset the bits in each symbol. Each shifted bit sequence is allocated into subcarriers of an OFDM symbol over a frequency range indicative of an operating frequency band of a domain to form the respective OFDM symbol. The set of OFDM symbols is transformed into a time domain signal for transmission.

Abstract: A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.