Abstract: A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.

Abstract: A remote plasma generator, coupling microwave frequency energy to a gas and delivering radicals to a downstream process chamber, includes several features which, in conjunction, enable highly efficient radical generation. In the illustrated embodiments, more efficient delivery of oxygen and fluorine radicals translates to more rapid photoresist etch or ash rates. A single-crystal, one-piece sapphire applicator and transport tube minimizes recombination of radicals in route to the process chamber and includes a bend to avoid direct line of sight from the glow discharge to the downstream process chamber. Microwave transparent cooling fluid within a cooling jacket around the applicator enables high power, high temperature plasma production. Additionally, dynamic impedance matching via a sliding short at the terminus of the microwave cavity reduces power loss through reflected energy. At the same time, a low profile microwave trap produces a more dense plasma to increase radical production.

Abstract: A welding system and method of use which allows a single welding operator to perform quick, easy and high quality vertical welds. The welding system comprises a welding fixture with a pair opposing, positionally adjustable welding shoes, and lock screws for attaching to a workpiece such as an I-beam. The welding fixture is located adjacent the end of an articulating boom, and a welding torch and oscillator are included on the welding fixture. A rotary straight wire feeder removes the cant and helix from welding wire as it is fed to the welding torch. The welding torch prevents welding wire from fusing to a guide tube in a manner which would interrupt a welding operation. The invention includes a distributed welding control system comprising a plurality of controller modules interfaced with a common bus. The control system allows a welding operator to program automated welding cycles for various welding operations.

Abstract: A remote plasma generator, coupling microwave frequency energy to a gas and delivering radicals to a downstream process chamber, includes several features which, in conjunction, enable highly efficient radical generation. In the illustrated embodiments, more efficient delivery of oxygen and fluorine radicals translates to more rapid photoresist etch or ash rates. A single-crystal, one-piece sapphire applicator and transport tube minimizes recombination of radicals in route to the process chamber and includes a bend to avoid direct line of sight from the glow discharge to the downstream process chamber. Microwave transparent cooling fluid within a cooling jacket around the applicator enables high power, high temperature plasma production. Additionally, dynamic impedance matching via a sliding short at the terminus of the microwave cavity reduces power loss through reflected energy. At the same time, a low profile microwave trap produces a more dense plasma to increase radical production.

Abstract: Workpieces, such as, semiconductor wafers, are continuously manufactured by repetitively alternately switching a common radio frequency power source between a plurality of downstream or in-chamber processing reactors and actively processing one workpiece in a vacuum in an operating one of the processing chambers while simultaneously executing with a robot at atmospheric pressure the overhead tasks relative to next processing another workpiece in the other processing chamber. The active processing of the workpieces in alternate chambers does not overlap, and the robot starts and completes all of its preparatory tasks during the active processing step during the time when a chamber's door is closed thereby providing virtual zero overhead. System architecture allows eliminating all redundant components other than the dual chambers which operate in parallel. For a modest cost increase for the second chamber throughput is trebled and overall costs significantly reduced.

Abstract: The present invention is an automated system to input text, audio and video data, to integrate the storage of the data at a central location, to initiate queries of search criteria to the central location from remote locations, and to dynamically transmit text, audio and video data to the remote locations in accordance with the search criteria.

Abstract: Apparatus and methods for AC power regulation primarily intended for inductive loads (e.g., fluorescent lights, motors, etc.) which provide substantial reduction in power consumption while also providing a leading power factor, reduced harmonic distortion, reduced crest factor and reduced noise. The system is self-adjusting for a wide range of loads and can reduce power consumption by 25 percent in lighting loads while producing minimal reduction in light output. The system utilizes a Triac and parallel capacitor bank in series with the load. The Triac is turned on in response to a near-zero differential voltage measured across the Triac and is turned off near the peak of each AC half cycle by shunting current around the Triac. The capacitor absorbs the inductive turn-off voltage spike caused by the collapsing magnetic field in the ballast at the instant of Triac turn-off. This energy, in turn, provides longer on-period for the lamp, thereby permitting more light and increased operating efficiency.

Abstract: An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

Abstract: A standard SNMP management station is replaced by a client computer having a standard Web browser while utilizing the services of a Web/SNMP proxy agent in accordance with the present invention. The Internet locations of the ASN.1 specifications for various MIB modules, as well as other information resources associated with those MIB modules, are stored in resource records in a section of the DNS established for storing such information. The Web/SNMP proxy agent automatically locates the ASN.1 specification for each MIB module of any identified SNMP agent, by looking up the location in the DNS. The Web/SNMP proxy agent then compiles the ASN.1 MIB module specifications into HTML documents for viewing on the client computer. User requests for retrieving data from specified MIB objects and/or for sending data values to specified MIB objects are communicated from the client computer to the Web/SNMP proxy agent using standard HTTUP communications.

Abstract: A low power, low noise driving circuit for a bank of LEDs utilized in the station units of the MAN system is provided by coupling each bank of LEDs in a series circuit between the voltage supply and a constant current source. Each LED has a controllable logic switch in parallel across it and the switches are further in series circuit with each other to form a ladder network. Any selected LED may be turned off by closing its corresponding logic switch. The current continues to flow then through the shunting switch into the remaining LEDs in the series circuit that are on. A plurality of such ladder networks may be coupled in parallel with each other and each ladder network controlled by a switching gate which selectively couples it to the constant current source so that the LED ladder networks are operated at a predetermined duty cycle.

Abstract: Incremental values of a plurality of capacitors are programmably coupled through ROM core FETs with selective threshold voltages, EPROM core FETs, RAM cells, ROM fuse links or antifuse ROM links to a dummy bit line. The dummy bit line carries a bit line voltage to simulate either the worst case logical one or worst case logical zero within a read-only memory array of memory cells. The dummy bit line voltage is used as a control signal to a trigger circuit. The trigger circuit generates at the appropriate threshold a triggering signal used to control sense amplifiers coupled to the memory circuit. Therefore, by programmably altering the delay time on the dummy bit line, the read cycle of the memory can be programmably altered to either minimize the read time cycle to provide a fast, high quality memory product, or to maximize the read time cycle to provide for a slower but higher yield memory product at less expense.

Abstract: A method and system are disclosed for measuring a temperature of a body in a non-contact mode based on heat flux measurement. The system includes a temperature measurement apparatus to be positioned in close proximity to a body for measuring the temperature of the body. The temperature measurement apparatus comprises a thermally conducting element, a first and a second temperature sensor, and a temperature modulation arrangement. The first and second temperature sensors are mounted in the conducting element and each measures a temperature of the conducting element. The temperature modulation arrangement modulates the temperature of the conducting element until the temperatures at the first and the second temperature sensors are substantially the same. When these temperatures are equalized, heat flux into the conducting element is zero and the temperature of the conducting element represents the temperature of the body. The apparatus thus enables accurate non-contact temperature measurement of a body.

Abstract: The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware.

Abstract: The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage.

Abstract: The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.

Abstract: An improved precharge timing control is provided by turning off the first one of a series of precharge clocks PC0 by means of discharging a single dummy word line. The dummy word line is comprised of a plurality of dummy word line segments wherein each of the segments are charged in parallel, but discharged in series. The discharge time required of the plurality of word line segments is sufficient to allow discharge of an end of a selected word line in the read only memory to ground. Improved timing with good performance is achieved by turning off the earliest precharge clock PC0 among a series of precharge clocks PC0 and PC1, for example, so that an improved precharge time for the ROM core for a fast process parameter is realized.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.

Abstract: A load balancing arm is shown and described as having improved control including a programmable control element and electronic air regulation to provide precise and controllable lifting force on a load. The disclosed load balancing arm responds to slight operator applied force to aid in movement of the load in overcoming system hysteresis, friction and load inertia without requiring the operator to apply a sufficiently large magnitude force to overcome such counteracting forces in the system. The disclosed load balancing arm further includes automatic load weight detection sensors for accommodating variation in load weights while applying a lifting force to the load which substantially equals the weight of the load. This allows the operator to move the load freely throughout a work space.

Abstract: A code generation system to construct an asynchronous real-time controller for a real-time system with asynchronous subsystems is described. The system includes a software user interface to specify a functional description of a real-time system with asynchronous subsystems. The software user interface includes code construction elements selected from a functional library with a corresponding menu. The menu includes a start-up procedure selection option used to initialize parameters associated with the real-time system, a background procedure selection option to specify a control action to be executed in relation to the real-time system, and an interrupt procedure selection option to specify an operation to be performed in response to an asynchronous interrupt signal. Each of the selection options include a variable block definition tool to read and write values to global variables.

Abstract: The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active.