Abstract: A method of configuration controlling a hierarchy of data arrays is disclosed, each data array in the hierarchy having at least one version, each version of each data array in the hierarchy being associated with one version of at least one other data array in the hierarchy, each data array comprising at least one data entry, each data entry comprising a plurality of fields, the plurality of fields comprising a version field and at least one characteristic field having a characteristic, the version field indicating which version of that data array the associated characteristic fields belong to. The method comprises the steps of: (i) defining a package of data arrays comprising a predetermined version of at least two data arrays in the hierarchy and in which at least one of the data arrays is to be updated to a new version based on a previous version; and (ii) appending a new version indicator indicative of the new version to each data entry having the previous version in the at least one of the data arrays.

Abstract: A signal of interest (SOI) may be selected from among a plurality of cochannel signals based on one or more internal or external structural feature/s of the SOI, e.g., automatically selected based on any one or more internal or external structural features of the SOI that is known a priori. Examples of such internal structural features include, but are not limited to, number, frequency and/or absolute or relative signal strength (signal to noise ratio) of one or more transmitted signal components (e.g., pilot tones, squelch tones, etc.) present in the SOI; absence of a signal component at a given frequency in the SOI (i.e., present as a “dead spot” at a given frequency within the SOI); signal strength versus frequency profile of the SOI, signal strength versus time domain profile of the SOI, transient characteristics, time versus frequency profile, etc.

Abstract: A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.

Abstract: An apparatus for covertly marking a target includes a housing sized and configured to simulate a portable electronic device; a reservoir positioned in the housing for holding a quantity of miniature markers; and a dispersing mechanism positioned in or on the housing for dispersing the markers onto the target.

Abstract: A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.

Abstract: A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

Abstract: An integrated circuit in communication with a host circuit includes an interconnect bus and a plurality of programmable elements. Each of the programmable elements includes a control interface for receiving a control signal, the control signal causing the memory element to selectively operate in one of a plurality of modes. In a first mode, the memory element communicates stored data to the output port upon receiving the control signal; in a second mode the memory element communicates stored data to the output port upon detecting valid data at the input port; in a third mode the memory element stores a first data value consisting of at least a portion of a single data word received at the input port; and in a fourth mode the memory element stores a second data value consisting of at least a portion of each of two separate input values received at the input port. Each programmable element may write data to and read data from a memory element of any of the other programmable elements.

Abstract: A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

Abstract: The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of: evaluating a desired response for the system as a function of an amplitude of the system and a phase of the system; separating the phase of the system into a linear component and a non-linear component; performing a first optimization by minimizing a weighted error between a desired response for the system and a cascaded response for the system as a function of an equalizing filter and a phase slope so as to obtain at least one local smallest error E(?) as a function of phase slope; and once the local smallest error E(?) is known, performing a second optimization to locate any existing global smallest error, wherein the global smallest error is within a set distance from the local smallest error.

Abstract: A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.

Abstract: A system and method for symbol rate estimation using vector velocity that does not require any prior knowledge of the signal's structure and is accurate in the presence of frequency offset and noise. An input signal is converted to a symbol constellation path signal, and a velocity signal representing a velocity of the symbol constellation path signal is generated. A first frequency spectrum of the velocity signal is generated by performing a Fast Fourier transform on the velocity signal, and a maximum peak value of the first frequency spectrum, a first bin below the maximum peak value, and a second bin above the maximum peak value are identified.

Abstract: A respirator helmet (10?) or other helmet adapted to receive, by means of a plug (66) and socket arrangement (70), a pivotable bar (62) carrying a protective screen (63) such that the screen may be moved between a lowered position in front of the face of the wearer of the helmet and a raised position.

Abstract: Systems and methods for managing operation of multiple tape drives in a way so that incoming data is spread or distributed across the multiple tape drives and which may be implemented in one example to continuously accept for recording without interruption from one or more data sources, for example, so that the date is distributed across the multiple tape drives in real time and without interruption as it becomes available from one or more given data sources. Two or more tape drives may be further be managed in a manner such that the multiple drives appear to be a single drive when writing data to, or reading data from, the multiple tape drives.

Abstract: One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A queue management system for e.g. supermarket checkouts uses counting devices located at checkouts and optimally entrances/exits in conjunction with P.O.S. information to produce a schedule of how many checkouts are needed to avoid queue length exceeding preset limits. The system includes a dynamic learning system which can optimise calculated schedules on the basis of historical data.

Abstract: An extensible binary mark-up language is disclosed that is compatible with existing XML standards yet provides significantly improved efficiencies for XML-based data storage and communications, particularly for narrow and low bandwidth communication media. A corresponding extensible non-binary mark-up language is also disclosed that is compatible with the XML standard. This dual-representation common message format (CMF) allows standard XML tools to be utilized in viewing and editing XML-based data and allows a CMF parser to be utilized to convert the XML formatted information into an extensible binary representation for actual communication through a medium or storage on a wide range of media.

Abstract: An optical data transceiver is manufactured by forming an integrated control circuit (101) on a suitable substrate, such as a silicon wafer, and then mounting said integrated circuit (101) onto the lead frame (102). Electrical connections may then be made between said integrated circuit (101) and said lead frame (102). The combined assembly comprising the integrated circuit (101) and lead frame (102) is then inserted into the cavity of a mold tool (not shown). A suitable molding compound is injected to encapsulate the combined assembly. The mold tool is provided with a projection (not shown) that is in contact with a portion of the surface of the integrated circuit (101) when the assembly is in the mold tool. As a result, the opening (106), exposing that portion of the surface of the integrated control circuit (101) that was in contact with the projection of the mold tool, is provided.

Abstract: A quadrature frequency division multiplexing (“OFDM”) wireless receiver, including methods and devices for adaptive quantization of OFDM signals according to modulation and coding schemes and sub-carrier frequency responses, is provided. Efficient quantization may be utilized to reduce the large dynamic range of signals to achieve circuit simplification and chip area reduction. In one embodiment, a quantization circuit includes a quantization selector to select quantization thresholds according to modulation and coding schemes and sub-carrier frequency responses, and a non-uniform quantizer to reduce input dynamic range so that an output is represented by fewer bits than an input.