Abstract: A light pattern projector with a pattern mask to spatially modulate an intensity of a wideband illumination source, such as an LED, and a projector lens to reimage the spatially modulated emission onto regions of a scene that is to be captured with an image sensor. The projector lens may comprise a microlens array (MLA) including a first lenslet to reimage the spatially modulated emission onto a first portion of a scene, and a second lenslet to reimage the spatially modulated emission onto a first portion of a scene. The MLA may have a fly's eye architecture with convex curvature over a diameter of the projector lens in addition to the lenslet curvature. The pattern mask may be an amplitude mask comprising a mask pattern of high and low amplitude transmittance regions. In the alternative, the pattern mask may be a phase mask, such as a refractive or diffractive mask.

Abstract: Techniques are provided for pre-processing enhancement of a speech signal. A methodology implementing the techniques according to an embodiment includes performing de-reverberation processing on signals received from an array of microphones, the signals comprising speech and noise. The method also includes generating time-frequency masks (TFMs) for each of the signals. The TFMs indicate the probability that a time-frequency component of the signal associated with that TFM element includes speech. The TFM generation is based on application of a recurrent neural network to the signals. The method further includes generating steering vectors based on speech covariance matrices and noise covariance matrices. The TFMs are employed to filter speech components of the signals, for calculation of the speech covariance, and noise components of the signals for calculation of the noise covariance.

Abstract: In multi-processor systems, some large jobs are performed by dividing the job into multiple tasks, having each task executed in parallel by separate nodes, and combining or synchronizing the results into a final answer. When communications between nodes represent a significant portion of total performance, techniques may be used to monitor and balance communications between the nodes so that the tasks will be completed at approximately the same time, thereby accelerating the completion of the job and avoiding wasting time and power by having some processors sit idle while waiting for other processors to catch up. Multiple synchronization points may be set up between the start and finish of task execution, to that mid-course corrections may be made.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Abstract: An apparatus is provided which comprises: a thermal sensor comprising one or more n-type devices or p-type devices that suffer from subthreshold factor variation, wherein the thermal sensor is to generate an output digital code representing a temperature; and a calibration circuitry coupled to the thermal sensor, wherein the calibration circuitry is to trim the effects of subthreshold factor variation from the output digital code.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: In some examples, a robot middleware system including a first robot middleware node, a second robot middleware node, and one or more secure encrypted type-enforced context message between the first robot middleware node and the second robot middleware node.

Abstract: A system may use memory tagging for side-channel defense, memory safety, and sandboxing to reduce the likelihood of successful attacks. The system may include memory tagging circuitry to address existing and potential hardware and software architectures security vulnerabilities. The memory tagging circuitry may prevent memory pointers from being overwritten, prevent memory pointer manipulation (e.g., by adding values), and increase the granularity of memory tagging to include byte-level tagging in cache. The memory tagging circuitry may sandbox untrusted code by tagging portions of memory to indicate when the tagged portions of memory include contain a protected pointer. The memory tagging circuitry provides security features while enabling CPUs to continue using and benefiting from speculatively performing operations.

Abstract: An embodiment of a semiconductor package apparatus may include technology to map a collection of data into two or more mathematical graph representations of the data based on a configurable set of rules that one of preserves or enhances relationships or properties of the data, and organize the two or more graph representations into two or more clusters of data based on graph information entropy and one or more parameters. Other embodiments are disclosed and claimed.

Abstract: A mechanism is described for facilitating multi-device reverberation estimation according to one embodiment. An apparatus of embodiments, as described herein, includes detection and capture logic to facilitate a microphone of a first voice-enabled device of multiple voice-enabled devices to detect a command from a user. The apparatus further includes calculation logic to facilitate a second voice-enabled device and a third voice-enabled device to calculate speech to reverberation modulation energy ratio (SRMR) values based on the command, where the calculation logic us further to estimate reverberation times (RTs) based on the SRMR values. The apparatus further includes decision and application logic to perform dereverberation based on the estimated RTs of the reverberations.

Abstract: Embodiments may relate to a polymer optical coupler. The polymer optical coupler may include a first portion at least partially coupled to a face of a silicon waveguide. The polymer optical coupler may further include a second portion of the polymer optical coupler that is adjacent to the first portion and which may have a width that is less than a width of the second portion opposite the first portion. Other embodiments may be described and/or claimed.

Abstract: Speech or non-speech detection techniques are discussed and include updating a speech pattern model using probability scores from an acoustic model to generate a score for each state of the speech pattern model, such that the speech pattern model includes a first non-speech state having multiple self loops each associated with a non-speech probability score of the probability scores, a plurality of speech states following the first non-speech state, and a second non-speech state following the speech states, and detecting speech based on a comparison of a score of the first non-speech state and a score of the last speech state of the multiple speech states.

Abstract: The present disclosure is directed to secure processing and display of protected content. The use of a trusted execution environment (TEE) to handle authentication and session key negotiation in accordance with a selected content protection protocol may reduce any trusted computing base (TCB) needed for such operations, and thereby present a smaller target for potential attackers. Techniques are presented in which a session key negotiated via such a TEE is securely provided to output circuitry such as a display controller, which may encrypt protected content that has been requested for viewing on a protocol-compliant display device communicatively coupled to a device comprising the TEE and/or the output circuitry. The output circuitry may then provide the encrypted protected content to the protocol-compliant display device, such as for compliant display of the protected content.

Abstract: Disclosed herein are fabrication techniques for providing metal gates in quantum devices, as well as related quantum devices. For example, in some embodiments, a method of manufacturing a quantum device may include providing a gate dielectric over a qubit device layer, providing over the gate dielectric a pattern of non-metallic elements referred to as “gate support elements,” and depositing a gate metal on sidewalls of the gate support elements to form a plurality of gates of the quantum device.

Abstract: The present disclosure is directed to systems and methods for preventing or mitigating the effects of a cache-timing based side channel attack, such as a Meltdown type attack. In response to a speculatively executed data access by an unretired or incomplete instruction, rather than transferring data to the CPU cache, the data is instead transferred to data transfer buffer circuitry where the data is held in the form of a record until the instruction requesting the data is successfully completed or retired. Upon retirement of the instruction requesting the data access, the data included in the record may be transferred to the CPU cache. Each record held in the data transfer buffer circuitry may include: a data source identifier; a physical/virtual address of the data; a cache line that includes the data; and an instruction identifier associated with the instruction initiating the data access.

Abstract: Techniques related to video encoding are discussed that, for each block of input video, select an individual partitioning and coding mode selection technique from multiple such selection techniques. For a picture, the selection algorithm takes as input scores for individual blocks, costs of the various partitioning and coding mode selection techniques, and various detector outputs. The selection algorithm provides as output a partitioning and coding mode selection technique for each block in picture. The algorithms selection is such that the overall cost of the selected algorithms in the picture is as close as possible to a given picture budget. Furthermore, a partitioning and coding mode selection algorithms, binary depth partitioning (BDP), is discussed. For a block, BDP provides fast convergence to a partitioning and associated coding modes first evaluating intermediate partitioning options and converging on the final partitioning by evaluating either larger of smaller partitions.

Abstract: In some embodiments, power may be temporarily removed from a first portion of a computer system (such as a display), and that power redirected to a second portion (such as a processor or System on a Chip), so that extra performance may be obtained from the second portion without exceeding the power budget for the system. If the first portion is a display, the time period of removed power may be short enough that the absence of luminance during that time period will not be noticeable to the human vision system. In a similar embodiment, power may be delivered to the first portion using pulse width modulation, using the time between pulses to redirect power to the other portion.

Abstract: A mechanism is described for facilitating automatic tuning of image signal processors using reference images in image processing environments, according to one embodiment. A method of embodiments, as described herein, includes one or more processors to: receive images associated with one or more scenes captured by one or more cameras; access tuning parameters associated with functionalities within an image signal processor (ISP) pipeline; generate reference images based on the tuning parameters, wherein a reference image is associated with an image for each functionality within the ISP pipeline; and automatically tune the ISP pipeline based on selection of one or more of the reference images for one or more of the images for one or more of the functionalities.

Abstract: A system may include a processor and a memory, the processor having at least one cache as well as memory access monitoring logic. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line includes several bits for storing information. During normal operation, the memory access monitoring logic may monitor for a memory access pattern indicative of a side-channel attack (e.g., an abnormally large number of recent CLFLUSH instructions). Upon detecting a possible side-channel attack, the memory access monitoring logic may implement one of several mitigation policies, such as, for example, restricting execution of CLFLUSH operations. Due to the nature of cache-timing side-channel attacks, this prevention of CLFLUSH may prevent attackers utilizing such attacks from gleaning meaningful information.

Abstract: The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry.