Patents Assigned to Intel Corporation
  • NEGATIVE CAPACITANCE FIELD EFFECT TRANSISTOR (NCFET) DEVICES
    Publication number: 20250006840
    Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: INTEL CORPORATION
    Inventors: Rachel A. Steinhardt, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Tristan A. Tronic, Ian Alexander Young, Matthew V. Metz, Marko Radosavljevic, Carly Rogan, Brandon Holybee, Raseong Kim, Punyashloka Debashis, Dominique A. Adams, I-Cheng Tung, Arnab Sen Gupta, Gauri Auluck, Scott B. Clendenning, Pratyush P. Buragohain, Hai Li
  • CROSS-NETWORK TIME-ALIGNMENT CHARACTERIZATION FOR SCHEDULED TRAFFIC
    Publication number: 20250007802
    Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Marcio Juliato, Javier Perez-Ramirez, Mikhail Galeev, Manoj Sastry, Dave Cavalcanti, Christopher Gutierrez, Shabbir Ahmed, Vuk Lesi
  • N-TYPE TRANSISTOR FABRICATION IN COMPLEMENTARY FET (CFET) DEVICES
    Publication number: 20250006812
    Abstract: N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: INTEL CORPORATION
    Inventors: Sudipto Naskar, Sukru Yemenicioglu, Abhishek Anil Sharma, Van Le, Weimin Han
  • Routing and Passive Components in a Direct Bonding Layer
    Publication number: 20250006630
    Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Carla Moran Guizan, Peter Baumgartner, Thomas Wagner, Georg Seidemann, Michael Langenbuch, Mamatha Yakkegondi Virupakshappa, Jonathan Jensen, Roshini Sachithanandan, Philipp Riess
  • HARDWARE-BASED CRYPTOGRAPHIC PROTECTION OF TOKENS
    Publication number: 20250005205
    Abstract: An example of an apparatus may include first circuitry that is to be selectively locked and unlocked, second circuitry to process one or more tokens including an unlock token for the first circuitry, and hardware authentication circuitry to authenticate the unlock token for the first circuitry in response to a request from the second circuitry. The apparatus may further include hardware ungate circuitry to selectively gate and ungate one or more features of the first circuitry in response to an indication that the first circuitry is one of locked or unlocked. Other examples are disclosed and claimed.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Iwan Grau, Anas Hlayhel, Santosh Ghosh, Sonal Waydande, Matthew Wise, William Penner, Enrico Carrieri
  • COMPUTE OPTIMIZATION MECHANISM
    Publication number: 20250005703
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.
    Type: Application
    Filed: July 15, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Adaptive Battery Usage Window to Extend Battery Longevity
    Publication number: 20250007017
    Abstract: Methods and apparatus relating to an adaptive battery usage window to extend battery longevity are described. In an embodiment, a State Of Charge (SOC) for a rechargeable battery is controlled based on a plurality of limited charging modes that may selectively allow/prevent charging/discharging of the rechargeable battery to target level(s). Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventor: Naoki Matsumura
  • METHODS AND APPARATUS TO PROVIDE RECOMMENDATIONS FOR DEVICE MANAGEMENT
    Publication number: 20250005457
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to provide recommendations for device management. An example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: determine an action to be performed for a plurality of computing devices, the action includes information about the computing devices and an operation to be performed on the computing devices; compare the action with a plurality of prior actions; and report a predicted result based on a similarity of the action with at least one of the plurality of prior actions.
    Type: Application
    Filed: August 30, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Mario Jose Divan Koller, Mariano Ortega De Mues, Marcos Emanuel Carranza, Cesar Ignacio Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, John Joseph Browne, Mats Gustav Agerstam, Gavin Bartlett Lewis, Abhishek Pillai, Tejaswini Sirlapu
  • ANTENNA MODULES WITH PARTIALLY OVERLAPPING STACKED CIRCUITS
    Publication number: 20250006719
    Abstract: Example antenna module includes antenna units provided over an antenna unit support, and ICs communicatively coupled to various antenna units. The ICs are arranged in two or more subsets of one or more ICs in each subset, where an individual IC belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ICs onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. When an average width of the ICs is larger than the average pitch of the antenna units, arranging the ICs in two or more subsets in different layers means that at least one of the ICs of one subset partially overlaps with at least one of the ICs of another subset.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Georgios Panagopoulos, Richard Geiger, Steven Callender, Georgios Dogiamis, Manisha Dutta, Stefano Pellerano
  • METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
    Publication number: 20250006610
    Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; and a magnetic material lining a first wall of a first opening in the first glass layer and lining a second wall of a second opening in the second glass layer.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Minglu Liu
  • HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED LAYER
    Publication number: 20250006806
    Abstract: In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Anand Murthy, Alexander Badmaev, Zhiyi Chen, Debaleena Nandi, Tahir Ghani
  • SCHEDULED-BASED LOW-LATENCY DETECTION FOR DESYNCHRONIZATION ATTACKS
    Publication number: 20250007738
    Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Christopher Gutierrez, Marcio Juliato, Manoj Sastry, Vuk Lesi, Shabbir Ahmed
  • MITIGATION OF THRESHOLD VOLTAGE SHIFT IN BACKSIDE POWER DELIVERY USING BACKSIDE PASSIVATION LAYER
    Publication number: 20250006579
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Avijit Barik, Tao Chu, Minwoo Jang, Aurelia Wang, Conor P. Puls
  • SERIAL INTERFACE PROVIDING ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20250006726
    Abstract: An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Krzysztof Domanski, Harshit Dhakad
  • METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
    Publication number: 20250006611
    Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example integrated circuit (IC) package includes: a package core including a first glass sheet and a second glass sheet distinct from the first glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) from the second glass sheet; a first redistribution layer on a first side of the package core; a second redistribution layer on a second side of the package core, the second side opposite the first side; and an interconnect extending through the package core, the interconnect including a magnetic material.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Minglu Liu
  • TECHNOLOGIES FOR BARRIER LAYERS IN PEROVSKITE TRANSISTORS
    Publication number: 20250006841
    Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Arnab Sen Gupta, Dmitri Evgenievich Nikonov, John J. Plombon, Rachel A. Steinhardt, Punyashloka Debashis, Kevin P. O'Brien, Matthew V. Metz, Scott B. Clendenning, Brandon Holybee, Marko Radosavljevic, Ian Alexander Young, I-Cheng Tung, Sudarat Lee, Raseong Kim, Pratyush P. Buragohain
  • STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATERIALS
    Publication number: 20250006737
    Abstract: A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Aryan Navabi-Shirazi, Michael Babb, Kai Loon Cheong, Cheng-Ying Huang, Mohammad Hasan, Leonard P. Guler, Marko Radosavljevic
  • METHODS AND APPARATUS FOR POWER DELIVERY THROUGH PACKAGE SUBSTRATES WITH STACKS OF GLASS LAYERS HAVING DIFFERENT COEFFICIENTS OF THERMAL EXPANSION
    Publication number: 20250006612
    Abstract: Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Minglu Liu
  • AUTO-PREDICATION FOR LOOPS WITH DYNAMICALLY VARYING INTERATION COUNTS
    Publication number: 20250004775
    Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. In an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Zeshan Chishti, Jeffrey Cook, Thomas McDonald
  • PHOTONIC INTEGRATED CIRCUIT WITHIN A CAVITY OF INTERPOSER
    Publication number: 20250004223
    Abstract: An apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Xiaoqian Li, Vidya Jayaram, Ravindranath V. Mahajan, Saikumar Jayaraman