Abstract: Methods and systems to improve a visual perception of dark scenes in video. An example device includes one or more processors to receive a frame of video segmented into a plurality of sub-regions. A local luminance histogram is generated for each sub-region. A global luminance histogram is generated for the entire frame of video and a global tone mapping curve is generated based on the global luminance histogram. A tone mapping LUT is generated for each sub-region based on the global tone mapping curve and the corresponding local luminance histogram for the sub-region. The frame of video is then modified using the tone mapping LUTs generated for each sub-region and sent to an output device.
Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.
Type:
Grant
Filed:
December 26, 2020
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Kameran Azadet, Wee Liew, Ramani Tatikola, Edwin Thaller, Patrick Torta, Yu-Shan Wang, Georg Weber, James Yoder
Abstract: An apparatus of a Wi-Fi station (STA), the apparatus including a radio frequency (RF) interface, and one or more processors coupled to the RF interface configured to: receive a first periodic training field and a second periodic training field of a preamble of a data packet; compare the first periodic training field of the preamble with the second periodic training field of the preamble; determine a first spurious tone parameter based on the comparison; receive a transmission frame of the data packet; determine a second spurious tone parameter based on the transmission frame of the data packet; and generate a frequency adjustment based on the first spurious tone parameter and the second spurious tone parameter.
Abstract: A board-to-board connector includes electrical leads to bridge from one board to another board, to interconnect pads on one surface of the boards. The boards can interconnect while aligned in substantially the same plane with an inline connector. The connector includes a lead frame having the electrical leads and the connector includes an alignment frame to hold the lead frame. The connector includes a conductive case to secure over the alignment frame. The connector includes screw holes to allow screws to secure the connector in place against the boards and ensure electrical connection between the pads on the two boards through the electrical leads of the connector. The alignment frame includes posts to mate with alignment holes in the boards.
Abstract: Systems, apparatuses, methods, and computer-readable media, are provided for selecting edge or central servers for serving client systems based on network events monitored by one or more network elements. Embodiments may be relevant to multi-access edge computing (MEC) and Automotive Edge Computing Consortium (AECC) technologies. Other embodiments may be described and/or claimed.
Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.
Type:
Grant
Filed:
January 23, 2023
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Robert Valentine, Menachem Adelman, Milind B. Girkar, Zeev Sperber, Mark J. Charney, Bret L. Toll, Rinat Rappoport, Jesus Corbal, Stanislav Shwartsman, Dan Baum, Igor Yanover, Alexander F. Heinecke, Barukh Ziv, Elmoustapha Ould-Ahmed-Vall, Yuri Gebil, Raanan Sade
Abstract: The present disclosure is directed at pairing a host electronic device with a peripheral electronic device using visual recognition and deep learning techniques. In particular, the host device may receive an indication of a peripheral device via a camera or as a result of searching for the peripheral device (e.g., due startup of a related application or periodic scanning). The host device may also receive an image of the peripheral device (e.g., captured via the camera), and determine a visual distance to the peripheral device based on the image. The host device may also determine a signal strength of the peripheral device, and determine a signal distance to the peripheral device based on the signal strength. The host device may pair with the peripheral device if the visual distance and the signal distance are approximately equal.
Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
Abstract: Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.
Type:
Grant
Filed:
June 26, 2020
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong
Abstract: An example apparatus for encoding immersive video includes a view optimizer to receive a plurality of input views from a source camera and select basic views and additional views from the plurality of input views. The apparatus also includes a view pruner to prune the additional views based on a comparison with the basic views. The apparatus further includes a patch packer to generate atlases based on the pruned additional views and the basic views. The apparatus includes a metadata composer to generate metadata including additional metadata. The apparatus also further includes a bitstream generator to generate a bitstream including the encoded video and the metadata.
Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
Type:
Grant
Filed:
May 24, 2023
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Praveen Kumar Gupta, Avinash N. Ananthakrishnan, Eugene Gorbatov, Stephen H. Gunther
Abstract: Methods and apparatus to adaptively manage data collection devices in distributed computing systems are disclosed. Example disclosed methods involve instructing a first data collection device to operate according to a first rule. The example first rule specifies a first operating mode and defining a first event of interest. Example disclosed methods also involve obtaining first data from the first data collection device while operating according to the first rule. Example disclosed methods also involve, in response to determining that the first event of interest has occurred based on the first data, providing a second rule based on the first data to the first data collection device, and providing a third rule to a second data collection device. The example second rule specifies a second operating mode and defines a second event of interest, and the examples third rule specifies a third operating mode.
Type:
Grant
Filed:
October 21, 2022
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Tao Zhong, Gang Deng, Zhongyan Lu, Kshitij Doshi
Abstract: A stiffener for an integrated circuit (IC) package assembly including an IC die electrically interconnected to a substrate. The stiffener is to be mechanically attached to the substrate adjacent to at least one edge of the IC die and have a coefficient of linear thermal expansion (CTE) exceeding that of the substrate. The stiffener may be an “anti-invar” metallic alloy. Anti-invar alloys display “anti-invar” behavior where thermal expansion of the material is significantly enhanced relative to other compositions of the particular alloy system. A package stiffener may be a high-Mn steel, for example, such as ASTM International A128. In other examples, a package stiffener is a MnCuNi, FeNiMn, or FeNiCr alloy having an average CTE over a range of 25-100° C. of at least 18 ppm, and a room temperature modulus of elasticity of at least 120 GPa.
Type:
Grant
Filed:
March 4, 2021
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Valery Ouvarov-Bancalero, John Harper, Malavarayan Sankarasubramanian, Patrick Nardi, Bamidele Daniel Falola, Ravi Siddappa, James Mertens
Abstract: For example, a wireless communication device may be configured to, based on a grouping criterion, select from a plurality of STAs a group of two or more STAs for a Trigger-Based (TB) Multi-User (MU) UL OFDMA control frame transmission to be communicated from the group of two or more STAs to the wireless communication device, the grouping criterion based on two or more RSSI values corresponding to the two or more STAs, respectively; to transmit a trigger frame to trigger the TB MU UL OFDMA control frame transmission, the trigger frame including two or more STA Identifiers to identify the two or more STAs, respectively; and to process the TB MU UL OFDMA control frame transmission from the group of two or more STAs, the TB MU UL OFDMA control frame transmission including two or more control frames from the two or more STAs, respectively.
Type:
Grant
Filed:
September 26, 2019
Date of Patent:
December 31, 2024
Assignee:
INTEL CORPORATION
Inventors:
Alexander W. Min, Rath Vannithamby, Arjun Anand, Vinod Kristem
Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
Type:
Grant
Filed:
August 16, 2021
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.
Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.
Type:
Grant
Filed:
March 25, 2021
Date of Patent:
December 31, 2024
Assignee:
Intel Corporation
Inventors:
Abhishek A. Sharma, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Rajat Paul
Abstract: A digital signal processing (DSP) block includes a plurality of multipliers and a summation block separate from the plurality of multipliers. The DSP block is configurable to perform a first multiplication operation to determine a first product of a first floating-point value and a second floating-point value using only a first multiplier of the plurality of multipliers. Additionally, the DSP block is configurable to perform a second multiplication operation between a third floating-point value and a fourth floating-point value by receiving, at each of the plurality of multipliers, two integer values generated from the third floating-point value and the fourth floating-point value, generating, via the plurality of multipliers, a plurality of subproducts by multiplying, at each of the multipliers, the two integer values, and generating a second product of the second multiplication operation by adding, via the summation block, the plurality of subproducts.
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to enable secure memory sharing in a multi-tenant edge network. Examples disclosed herein include mapping a first node to a memory region in response to receiving a memory access request from a second node mapped to the memory region, providing a private security key associated with the memory region to the first node, and applying a cache coherency protocol to the first node and the second node in response to the pooled memory controller mapping the first node to the memory region.