Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

Abstract: Systems, apparatuses and methods may provide for technology that aggregates contextual information from a first network layer in a neural network having a second network layer coupled to an output of the first network layer, wherein the context information is to be aggregated in real-time and after a training of the neural network, and wherein the context information is to include channel values. Additionally, the technology may conduct an importance classification of the aggregated context information and selectively exclude one or more channels in the first network layer from consideration by the second network layer based on the importance classification.

Abstract: Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example package substrate includes: a first glass layer including a first through glass via extending therethrough, the first glass layer having a first coefficient of thermal expansion (CTE); and a second glass layer including a second through glass via extending therethrough, the second glass layer having a second CTE different from the first CTE, the first through glass via electrically coupled to the second through glass via.

Abstract: An integrated circuit (IC) device includes an IC die on a substrate, and the substrate includes a group of conductive lines between a high-permittivity dielectric layer and a low-permittivity dielectric layer, with a ground plane separated from the conductive lines by either the high- or low-permittivity dielectric layer. The substrate may include other low-permittivity dielectric layers. The substrate may include other groups of conductive lines between ground planes. The high-permittivity dielectric layer may be within a low-permittivity dielectric core layer.

Abstract: Systems and methods for receive-side customization of presentation of mixed media data. Systems and methods focus on the receive path so that each participant in a video conference or other mixed media application can, as a receiver of mixed media data signals, customize the individual incoming mixed media data signals for display on the receiver's user device. User customization options include blocking video or avatars, converting (to avatars), and filtering distracting behavior. Embodiments enable all participating users (not just a host user) to respectively receive-side customize the presentation/display of the mixed media data. Additionally, systems and methods can be implemented in an existing server.

Abstract: Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.

Abstract: Techniques for error correction with memory safety and compartmentalization are described. In an embodiment, an apparatus includes a processor to provide a first set of data bits and a first tag in connection with a store operation, and an error correcting code (ECC) generation circuit to generate a first set of ECC bits based on a first set of data bits and a first tag.

Abstract: Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

Abstract: Technologies for hybrid optical chip-to-chip coupling are disclosed. In an illustrative embodiment, light from a waveguide in a photonic integrated circuit (PIC) die is collimated using a micromirror and directed towards a glass substrate. Another micromirror in the glass substrate focuses the light into a waveguide defined in a bulk layer of the glass substrate. In the illustrative embodiment, the waveguide is directly written into the bulk layer using an ultrafast laser. The glass substrate also has waveguides with a large difference in the index of refraction in a layer above the bulk substrate, such as silicon nitride waveguides in silicon oxide cladding. The directly-written waveguides can be evanescently coupled to the silicon nitride waveguides. The silicon nitride waveguides can then be used for two-dimensional routing throughout the glass substrate. The light can be coupled back into a directly-written waveguide before it is transmitted to another PIC die.

Abstract: Systems, apparatus, articles of manufacture, and methods for stacks of glass layers including deep trench capacitors are disclosed. An example substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer coupled to the first glass layer, and a deep trench capacitor embedded in the first core.

Abstract: Embodiments of optical adapters, and methods of forming and using the same, are disclosed herein. In one example, an optical adapter includes a first interface to mate with a first optical connector, a second interface to mate with a second optical connector, and a plurality of waveguides extending through the optical adapter from the first interface to the second interface. The first interface includes a first set of alignment features to align the optical adapter with the first optical connector, and the second interface includes a second set of alignment features to align the optical adapter with the second optical connector. Further, when the first interface is mated with the first optical connector and the second interface is mated with the second optical connector, the first and second optical connectors are optically coupled via the waveguides.

Abstract: A method for manufacturing integrated circuit (IC) devices includes forming first and second mask patterns with overlapping and non-overlapping features. Non-overlapping features may be removed before etching a target material layer. A third mask pattern may be formed from the overlapping features and used to etch a target material layer. The third mask pattern may be employed to make regular arrays of substantially rectangular structures. An IC device may include an IC die, an array of structures on a layer of the IC die, and multiple groups of parallel stripes of indentations or depressions in the layer. The structures may each include a transistor and a capacitor.

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

Abstract: A system for reducing bandwidth and/or reducing power consumed by a display may comprise a display having a background plane and a region of interest plane that may be identified by a gaze tracker. The region of interest may be of a higher quality picture. In some embodiments, the display may be a large panel display and in others a head mounted display (HMD).

Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

Abstract: A method comprises receiving, from a remote device, an audio/video input signal, identifying one or more objects in the audio/video input signal tagged as a sensitive object, evaluating a set of workload requirements for a set of processing workloads comprising portions of the audio/video input signal, selecting one or more heavy processing workloads in the set of processing workloads to send to a compute service provider, in response to a determination that the one or more heavy processing workloads comprises one or more objects tagged as a sensitive object, encrypting the one or more objects tagged as a sensitive object using a homomorphic encryption protocol to generate a first homomorphically encrypted string, and sending the first homomorphically encrypted string to the compute service provider via a privacy protected communication channel.

Abstract: Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.

Abstract: Techniques related to video coding include content adaptive quantization that provides a selection between objective quality and subjective quality delta QP offsets.