Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

Abstract: Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Abstract: A platform health engine for autonomous self-healing in platforms served by an Infrastructure Processing Unit (IPU), including: an analysis processor configured to apply analytics to telemetry data received from a telemetry agent of a monitored platform managed by the IPU, and to generate relevant platform health data; a prediction processor configured to predict, based on the relevant platform health data, a future health status of the monitored platform; and a dispatch processor configured to dispatch a workload of the monitored platform to another platform managed if the predicted future health status of the monitored platform is failure.

Abstract: Apparatuses, methods and storage medium associated with in-vehicle computing, are disclosed herein. In embodiments, an in-vehicle system computing platform having a hypervisor to host one or more virtual machines (VMs) includes a memory shrink manager, and a memory snapshot manager. The memory shrink manager is configured to orchestrate shrinking a memory footprint of one of the one or more VMs for a suspend process invoked in response to the computing platform being powered off. The memory snapshot manager is configured to save the shrunken memory footprint of the one VM to the persistent storage during the suspend process, and to reload a subset of the saved shrunken memory footprint during a resume process to resume the one VM from suspension to the persistent storage. The resume process is invoked in response to the computing platform being powered on, cold booted.

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

Abstract: Provided herein are apparatus and methods for signaling regulatory information and transmit power information for device-to-device communication. An apparatus for a Wi-Fi device comprising: a RF interface; and processor circuitry coupled with the RF interface. The processor circuitry is to: decode a first discovery frame received from a peer Wi-Fi device via the RF interface to obtain a first Operation Information attribute of the peer Wi-Fi device, wherein the first Operation Information attribute is to indicate a first operation mode of the peer Wi-Fi device; and encode, in response to the first discovery frame, a second discovery frame for transmission to the peer Wi-Fi device via the RF interface, wherein the second discovery frame includes a second Operation Information attribute of the Wi-Fi device to indicate a second operation mode of the Wi-Fi device. Other embodiments may also be disclosed and claimed.

Abstract: A system, article, device, apparatus, and method of binaural audio emulation comprises receiving, by processor circuitry, multiple audio signals from multiple microphones and overlapping in a same time and associated with a same at least one audio source. The method also comprises generating binaural audio signals comprising inputting at least one version of the multiple audio signals into a neural network.

Abstract: A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.

Abstract: Heat exchange apparatuses and methods for hyperbaric cooling fan applications such as computing devices. The apparatus comprises a material with high thermal conductivity and is configured to be overlaid on an internal surface of the housing, such that an internal surface of the apparatus is exposed to the hot air flowing inside the housing, and an external surface of the apparatus occludes at least some of the existing through-holes of the housing. In operation, the apparatus converts the through-holes into passive heat exchanging regions that passively transfer heat from inside the housing to outside the housing, which brings the internal air temperature and junction temperature (Tj) of the heat generating components down. Provided embodiments do not require reworking of the original industrial design (ID) of the housing.

Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: An integrated circuit device includes an electrostatic discharge (ESD) protection circuit comprising a plurality of P+/N-well diodes (P-diodes) and a plurality of N+/P-well (N-diodes) arranged in a stripe geometry, a p-tap anode stripe of the ESD protection circuit shared between a first P-diode and a second P-diode of the ESD protection circuit, and a n-tap cathode stripe of the ESD protection circuit shared between a first N-diode and a second N-diode of the ESD protection circuit. Other examples are disclosed and claimed.

Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.

Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

Abstract: An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.