Abstract: Integrated circuit interconnect structures including an interconnect metallization feature comprising a sidewall reacted with a chalcogen into a low resistance liner. A portion of a backbone material or a metal seed layer may be advantageously converted into a metal chalcogenide, which can lower scattering resistance of an interconnect feature relative to alternative diffusion barrier materials, such a tantalum. Scattering resistance of such metal chalcogenide liner materials may be further reduced by actively cooling an IC, for example to cryogenic temperatures.

Abstract: Integrated circuit dies, systems, and techniques, are described herein related to junction field effect transistors operable at low temperatures and low voltages. A system includes an integrated circuit die deploying a junction field effect transistor that includes a source, a drain, and a gate structure coupled to a multi-layer quantum well. The source and drain are indium arsenide and the gate structure includes a high-k gate dielectric material. The system further includes a cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve a low operating temperature of the integrated circuit die.

Abstract: For example, a transmitter, e.g., for a wireless communication device, may be configured to transmit a wideband Radio Frequency (RF) Transmit (Tx) signal having a wide bandwidth of at least 80 Megahertz (MHz). For example, the transmitter may be configured to generate the wideband RF Tx signal having the wide bandwidth based on a baseband signal. The transmitter may be configured to generate the wideband RF Tx signal including a suppressed third harmonic and a suppressed fifth harmonic.

Abstract: A method of performing ring allreduce operations is disclosed. The method includes sending a chunk of a message in a receive buffer at a current index of a send buffer to a next node in a virtual ring of nodes, receiving a chunk of the message from a previous node in the virtual ring of nodes and store the chunk at the current index of the receive buffer, and reducing a chunk in a send buffer at a previous index of the receive buffer and a chunk in the receive buffer at a previous index of the receive buffer and storing a result at the previous index of the receive buffer. The method includes repeating the sending, receiving and storing, and reducing and storing steps until all chunks of the message are reduced, and sending reduced chunks to the next node and receive reduced chunks from the previous node.

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Abstract: For example, a first Access Point (AP) may be configured to send a plurality of data packets to a second AP via a backhaul link between the first AP and the second AP; to determine a plurality of identified packets from the plurality of data packets for a joint transmission to a non-AP wireless communication station (STA) associated with the first AP; to transmit a multi-AP trigger frame to trigger the joint transmission including transmission of the plurality of identified packets in a first transmission from the first AP and in a second transmission from the second AP, wherein the multi-AP trigger frame includes payload-signaling information configured to signal to the second AP that a payload of the second transmission is to include the plurality of identified packets; and to transmit the first transmission after the multi-AP trigger frame, wherein the first transmission includes the plurality of identified packets.

Abstract: Thermoelectric (TE) devices and their manufacture on integrated circuit (IC) dies to improve thermal performance. An IC die may include a substrate with transistors on one side, a heat spreader on a second side, and a TE device between them. The TE device may have TE elements with similar dimensions as transistor features. An IC die with transistor circuitry blocks in multiple areas of an IC die may include TE devices between each of the transistor circuitry blocks and a heat spreader.

Abstract: A modification structure may be formed within a chassis of an electronic product to improve its thermal dissipation systems, to lessen its weight, and/or to enhance its durability, while maintaining the industrial design/esthetics/ergonomics thereof, wherein the modification structure may comprise a plurality of fused modification material particles. The modification structures may have a higher thermal conductivity than the chassis, may have a lower thermal conductivity than the chassis, may have a lower density than the chassis, and/or may have a higher yield strength than the chassis. In a specific example, the modification structure may extend entirely through the chassis and be sufficiently porous to allow air flow to assist in heat dissipation from the electronic product.

Abstract: Technologies for liquid metal mixtures for electrical interconnects are disclosed. In the illustrative embodiment, a gallium mixture includes gallium or gallium alloy mixed with fine particles of, e.g., gallium oxide. The fine particles change properties of the gallium or gallium alloy, such as the viscosity, surface tension, and surface bonding. As a result of the changes caused by the fine particles, the gallium mixture can be more easily integrated into electrical interconnects, such as by using screen printing techniques. In one embodiment, the gallium mixture may form an array of interconnects on an integrated circuit component for connecting to another integrated circuit component.

Abstract: An apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. The apparatus includes a graphics processing unit having a data management unit (DMU) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. Processing circuitry is coupled to the DMU. The processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.

Abstract: Integrated circuit (IC) including domino logic circuit blocks with nFETs that are implemented in a first device layer and pFET keeper transistors that are implemented in a second device layer. The multiple device layers may be integrated within an IC die through layer transfer. Very low temperature operation (e.g., ?25° C., or less) may greatly reduce electrical leakage current from dynamic nodes of the domino logic circuit blocks so that output capacitance of the keeper transistors is sufficient to maintain dynamic node charge levels for good noise margin.

Abstract: This disclosure describes systems, methods, and devices related to extreme high throughput (EHT) data scrambler. A device may determine an extreme high throughput (EHT) data field of a frame to be scrambled using an EHT data scrambler. The device may determine to initialize the EHT data scrambler using an initialization seed, wherein the initialization seed has a size greater than seven bits. The device may generate scrambled data using the initialization seed. The device may cause to send the frame comprising the scrambled data to a first station device.

Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

Abstract: Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmis¬ sion channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

Abstract: Systems and methods for measurement and reporting of average UL and DL delays and delay distributions for an NG-RAN and UPF, as well as gNB-DU DL latency, for the N3 and N9 interfaces, internal UPF delay, and between the PSA UPF and NG-RAN and between the PSA UPF and UE are described. For the UL and DL average delay and delay distributions, the measurements are split into subcounters per 5QI/QCI, S-NSSAI and/or DSCPs, with the delay distributions subcounters in bins with discrete delay ranges. The measurements aon the N3 interface delay are also differentiated between a PSA UPF and an I-UPF.

Abstract: Example predictive wireless feedback control systems disclosed herein include a receiver to receive measurements of a controlled system via a first wireless link. Disclosed example systems also include an observer to output estimated values of states of the controlled system based on a state space model that is updated based on the measurements. Disclosed example system further include a predictor to predict future values of the states of the controlled system based on the estimated values of the states, a first latency of the first wireless link and an upper limit of a second latency associated with a second wireless link that is to communicate values of a control signal to an actuator associated with the controlled system. In disclosed examples, the predictor is to output the predicted future values of the states to a controller that is to determine the control signal.

Abstract: Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes instructions, and at least one processor to execute the instructions to determine whether a GPU supports modification of entry point addresses, detect a first entry point address and a second entry point address of an original GPU kernel, create a corresponding instrumented GPU kernel from the original GPU kernel based on the determination by inserting at least one of first profiling initialization instructions or first jump instructions at the first entry point address of the instrumented GPU kernel, inserting at least one of second profiling initialization instructions or second jump instructions at the second entry point address of the instrumented GPU kernel, and inserting profiling measurement instructions into the instrumented GPU kernel.

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

Abstract: In one embodiment, an apparatus comprises a processor to read a data line from memory in response to a read request from a VM. The data line comprises encrypted memory data. The apparatus also comprises a memory encryption circuit in the processor. The memory encryption circuit is to use an address of the read request to select an entry from a P2K table; obtain a key identifier from the selected entry of the P2K table; use the key identifier to select a key for the read request; and use the selected key to decrypt the encrypted memory data into decrypted memory data. The processor is further to make the decrypted memory data available to the VM. The P2K table comprises multiple entries, each comprising (a) a key identifier for a page of memory and (b) an encrypted address for that page of memory. Other embodiments are described and claimed.

Abstract: This disclosure describes systems, methods, and devices related to secure location measurement sharing. A device may cause to send a first indication associated with a location of the device to a cloud server. The device may cause to send a second indication associated with a ranging information of an access point (AP), wherein the AP is connected to the cloud server. The device may identify an access token received from the cloud server, wherein the access token is associated with providing anonymized AP location information to the AP, and wherein the access token is associated with accessing channel allocation from a channel access database.