Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

Abstract: A three dimensional (3D) array of magnetic random access memory (MRAM) bit-cells is described, wherein the array includes a mesh of: a first interconnect extending along a first axis; a second interconnect extending along a second axis; and a third interconnect extending along a third axis, wherein the first, second and third axes are orthogonal to one another, and wherein a bit-cell of the MRAM bit-cells includes: a magnetic junction device including a first electrode coupled to the first interconnect; a piezoelectric (PZe) layer adjacent to a second electrode, wherein the second electrode is coupled to the second interconnect; and a first layer adjacent to the PZe layer and the magnetic junction, wherein the first layer is coupled the third interconnect.

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.

Abstract: Logic to perform a point of sale (POS) transaction as Card Present. Logic may communicate with a web site of an online vendor to process a payment to the online vendor as a certified POS device. Logic may communicate with a payment service provider associated with the online vendor to process the payment in response to communicating with the web site. Logic may interact with a card reader to obtain a packet to process the payment with a payment instrument to verify the presence of the payment instrument. Logic may encrypt communications to transmit an authorization request to the payment service provider to process the payment with encrypted communications via a secure element agent of the certified POS device, the authorization request to comprise the packet to verify that the payment instrument is present for the transaction. And logic may receive an approval of the authorization request for the payment.

Abstract: An apparatus to facilitate accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits is disclosed. The apparatus includes a processor comprising a re-encoder to re-encode a first input number of signed input numbers represented in a first precision format as part of a machine learning model, the first input number re-encoded into two signed input numbers of a second precision format, wherein the first precision format is a higher precision format than the second precision format. The processor further includes a multiply-add circuit to perform operations in the first precision format using the two signed input numbers of the second precision format; and a sparsity hardware circuit to reduce computing on zero values at the multiply-add circuit, wherein the processor to execute the machine learning model using the re-encoder, the multiply-add circuit, and the sparsity hardware circuit.

Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.

Abstract: Aspects of the embodiments include an edge card and methods of making the same. The edge card can include a printed circuit board (PCB) comprising a first end and a second end, the first end comprising a plurality of metal contact fingers configured to interface with an edge connector, and the second end comprising a through-hole configured to mate with a post of a screw, the PCB further comprising an aperture proximate the second end of the PCB. The PCB can also include a thermal conduction element secured to the PCB, the thermal conduction element supporting an integrated circuit package, the integrated circuit package received by the aperture, wherein the thermal conduction element contacts the PCB proximate the through-hole and the thermal conduction element is configured to conduct heat from the integrated circuit towards the second portion of the printed circuit board.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: Methods and apparatus for a distributed processing quality of service algorithm for system performance optimization under thermal constraints are disclosed. An example method includes transmitting, at a first time, a first kernel assignment to a system on chip, the first kernel assignment including an indication of a plurality of kernels assigned to a first sub-system of the system on chip, determining, at the first time, a temperature associated with hardware of the system on chip, when the temperature is above a threshold temperature, generating a second kernel assignment including an indication of a first subset of the plurality of kernels assigned to the first sub-system and an indication of a second subset of the plurality of kernels assigned to a second sub-system of the system on chip, and transmitting, at a second time later than the first time, the second kernel assignment to the system on chip.

Abstract: Apparatus and method to facilitate automatic detection of a device state are disclosed herein. Selectively constraining a sensor based data set associated with one or more states of a device, wherein selectively constraining the sensor based data set includes analyzing a distribution of the sensor based data set to determine whether to constrain the sensor based data set, the sensor based data set including a first class and a second class of data values. Determining a threshold associated with the sensor based data set by selecting the threshold based on a variance between the first and second classes of the sensor based data set, wherein selecting the threshold includes using a constrained sensor based data set when the sensor based data set is determined to be constrained, and wherein the threshold indicates the data values associated with the first and second classes.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.

Abstract: One embodiment provides an apparatus. The apparatus includes a first signal trace and a current return path. The current return path includes a plurality of portions. The plurality of portions includes a first portion, a second portion and a third portion. The first portion is included in a first power plane. The second portion is included in a second power plane coplanar with the first power plane and separated from the first power plane by a split. The third portion spans the split and is included in a reference voltage plane. The reference voltage plane is coplanar with the first signal trace. The reference voltage plane is separated from the first power plane and the second power plane by a dielectric material.

Abstract: Apparatuses, methods and storage medium associated with capturing images are described herein. In embodiments, an apparatus may include an image or video capturing application to capture one or more images using a camera worn on a user's head, that includes an orientation function to receive a collection of a plurality of sensor data, and process the collection of sensor data to determine desired and actual orientations of the camera, and a control function to control the camera, to delay or suspend activation of the camera, if the actual orientation is misaligned with the desired orientations of the camera in excess of a misalignment threshold. In embodiments, the one or more images may be part of a time series of images or videos. Other embodiments may be described and/or claimed.

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on?VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi ?Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

Abstract: Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.

Abstract: Embodiments of a Next Generation Vehicle-to-Everything (NGV) station (STA) and method of communication are generally described herein. The NGV STA may encode a physical layer convergence procedure (PLCP) protocol data unit (PPDU) for transmission in a dedicated short-range communication (DSRC) frequency band allocated for vehicular communication by NGV STAs and legacy STAs. In some cases, the NGV STA may encode the PPDU in accordance with an NGV enhanced physical (PHY) layer protocol, and includes usage of a mid-amble, space-time block coding (STBC), or low-density parity check (LDPC) coding. In other cases, the NGV STA may encode the PPDU in accordance with a legacy PHY layer protocol that is compatible with the legacy STAs, and excludes usage of the mid-amble, the STBC, and the LDCP coding.

Abstract: A device, method and system of video and audio sharing among communication devices, may comprise a communication device for generating and sending a packet containing information related to the video and audio, and another communication device for receiving the packet and rendering the information related to the audio and video. In some embodiments, the communication device may comprise: an audio encoding module to encode a piece of audio into an audio bit stream; an avatar data extraction module to extract avatar data from a piece of video and generate an avatar data bit stream; and a synchronization module to generate synchronization information for synchronizing the audio bit stream with the avatar parameter stream.