Abstract: The present disclosure provides privacy preservation of analytic workflows based on splitting the workflow into sub-workflows each with different privacy-preserving characteristics. Libraries are generated that provide for formatting and/or encrypting data for use in the sub-workflows and also for compiling a machine learning algorithm for the sub-workflows. Subsequently, the sub-workflows can be executed using the compiled algorithm and formatted data.

Abstract: Techniques related to accelerated video enhancement using deep learning selectively applied based on video codec information are discussed. Such techniques include applying a deep learning video enhancement network selectively to decoded non-skip blocks that are in low quantization parameter frames, bypassing the deep learning network for decoded skip blocks in low quantization parameter frames, and applying non-deep learning video enhancement to high quantization parameter frames.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a remote direct memory access (RDMA) message from a first virtual machine located on a first network element, determine that the RDMA message is destined for a second virtual machine that is located on the first network element, and use a local direct memory access engine to process the RDMA message, where the local direct memory access engine is located on the first network element. In an example, the electronic device can be further configured to determine that the RDMA message is destined for a third virtual machine on a second network element, wherein the second network element is different than the first network element and use an other device acceleration driver to process the RDMA message instead of the local direct memory access engine.

Abstract: An example apparatus for video frame segmentation includes a receiver to receive a current video frame to be segmented. The apparatus also includes a segmenting neural network to receive a previous mask including a segmentation mask corresponding to a previous frame and generate a segmentation mask for the current frame based on the previous mask and the video frame.

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.

Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

Abstract: Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

Abstract: Systems, apparatuses and methods may provide for technology that supplements a battery coupled to a processor configuration with stored energy from a charger input, wherein the battery is supplemented with the stored energy in response to an increased power demand on the battery. The technology may also initiate one or more throttle operations in the processor configuration if the increased power demand does not end before the stored energy is depleted. If the increased power demand ends before the stored energy is depleted, the one or more throttle operations may be bypassed. The increased power demand may correspond to a system voltage being below a voltage threshold, a battery current being above a current threshold, and so forth.

Abstract: A transceiver associated with a wireline communication system is disclosed. The transceiver comprises one or more processors configured to associate a quality of service (QoS) grade tag to each data packet of a plurality of data packets to be transmitted and assemble a data transfer unit (DTU) comprising one or more or a part of a data packet of the plurality of data packets, wherein the one or more or the part of the data packet are encapsulated into a plurality of DTU frames within the DTU. The one or more processors is further configured to associate a highest DTU tag to the assembled DTU, wherein the highest DTU tag is indicative of a highest QoS grade associated with the DTU frames of the assembled DTU; and determine a schedule for transmission or retransmission of the assembled DTU, based on the highest DTU tag of the assembled DTU.

Abstract: Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.

Abstract: An originated packet is to be forward-propagated along a path to a destination device, with the path including one or more intermediary node devices. A path quality indication representing a reported error having been detected by at least one of the intermediary node devices residing along the path, is incorporated in the forward-propagating packet. The destination device incorporates the path quality indication in an acknowledgement packet directed to the originator of the packet.

Abstract: A system includes a central processing unit (CPU) and components, a particular one of including logic to participate in a portion of a boot sequence of the system, where the portion of the boot sequence begins prior to activation of the CPU. The particular component is to send one or more signals to interact with another one of the components in the system during the portion of the boot sequence. The particular component includes a timer block to generate a set of timestamps during the portion of the boot sequence, where the set of timestamps indicates an amount of execution time of the particular component. The particular component sends the set of timestamps to the other component in a particular one of the one or more signals, where the set of timestamps are used to determine execution time of system components to complete the boot sequence.

Abstract: Embodiments herein relate to gas identification with a gas identification apparatus having a plurality of metal oxide semiconductor (MOS) sensors. In various embodiments, a gas identification apparatus may include a set of heterogeneous MOS sensors to provide different response patterns for the presence of different gases and an identification engine coupled with the sensors, and having a plurality of regression models and one or more artificial neural networks, to analyze a response pattern to identify presence of a gas, based at least in part on a plurality of property measurements of the MOS sensors when exhibiting the response pattern, and using one or more of the plurality of regression models and the one or more artificial neural networks. Other embodiments may be described and/or claimed.

Abstract: Devices, systems, and methods that reduce the latency of detecting that a codeword is uncorrectable are disclosed and described. Such devices, systems, and methods allow the determination that a codeword is uncorrectable prior to determining error locations in the codeword, thus eliminating the need for such an error location search.