Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.

Abstract: Some embodiments include apparatus and methods for using a switch to couple an inductor to an energy harvester for a time interval to allow charging of the inductor during the time interval, and using a circuit to generate control information for power management. A value of the control information is based on a value of the time interval.

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Abstract: An apparatus for wireless transmissions and reception. The apparatus includes a radio frequency (RF) circuitry, a baseband circuitry, and a conversion circuitry. The RF circuitry is configured to transmit and receive a signal in an RF frequency. The baseband circuitry is configured to process a transmit signal or a receive signal in a baseband frequency. The conversion circuitry is configured to perform frequency conversion between the baseband and RF frequencies. The conversion circuitry is configured to convert a baseband signal received from the baseband circuitry to an RF signal in a first RF frequency if a transmit frequency is a second RF frequency or to the RF signal in the second RF frequency if the transmit frequency is the first RF frequency, and send the RF signal after frequency conversion to the RF circuitry. The RF circuitry converts the received RF signal to the transmit frequency for transmission.

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract: Secure memory repartitioning technologies are described. Embodiments of the disclosure may include a processing device including a processing core and a memory controller coupled between the processor core and a memory device. The memory device includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core is to receive a non-secure access request to a page in the memory device, responsive to a determination, based on one or more secure state bits in one or more secure state bit arrays, that the page is a secure page, insert an abort page address into a translation lookaside buffer, and responsive to a determination, based on the one or more secure state bits in the one or more secure state bit arrays, that the page is a non-secure page, insert the page into the translation lookaside buffer.

Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.

Abstract: Particular embodiments described herein provide a display that includes a mask that includes a one or more exposed areas, a top electrode, one or more bottom electrodes, a dielectric between the top electrode and the one or more bottom electrodes, and an electrical connection to create a differential voltage between the top electrode and the one or more bottom electrodes.

Abstract: Techniques and screening messages based on tags in an automotive environment, such as, messages communicated via a communication bus, like the CAN bus. Messages can be tagged with either a binary or probabilistic tag indicating whether the message is fraudulent. ECUs coupled to the CAN bus can receive the messages and the message tags and can determine whether to fully consume the message based on the tag.

Abstract: In one embodiment, a processor includes a memory hierarchy and a core coupled to the memory hierarchy. The memory hierarchy stores encrypted data, and the core includes circuitry to access the encrypted data stored in the memory hierarchy, decrypt the encrypted data to yield decrypted data, perform an entropy test on the decrypted data, and update a processor state based on a result of the entropy test. The entropy test may include determining a number of data entities in the decrypted data whose values are equal to one another, determining a number of adjacent data entities in the decrypted data whose values are equal to one another, determining a number of data entities in the decrypted data whose values are equal to at least one special value from a set of special values, or determining a sum of n highest data entity value frequencies.

Abstract: A microcoded processor instruction may invoke a number of microinstructions to perform a round of a SHA3 operation using a circuit that includes a first stage circuit to perform a set of first bitwise XOR operations on a set of five input blocks to yield first intermediate output blocks; perform a set of second bitwise XOR operations on a first intermediate block and a rotation of another first intermediate block to yield second intermediate blocks; and perform a set of third bitwise XOR operations on a second intermediate block and an input block to yield third intermediate blocks. The circuit further includes a second stage circuit to rotate bits within each of the third intermediate blocks to yield a set of fourth intermediate blocks, and a third stage circuit to perform an affine mapping on bits within each of the fourth intermediate blocks to yield a set of output blocks.

Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.

Abstract: A phase change memory structure (100) includes a phase change material layer (110), a top electrode layer (120) above the phase change material layer, a metal silicon nitride layer (130) in contact with the top electrode layer opposite from the phase change material layer, a metal silicide layer (140) in contact with the metal silicon nitride layer opposite from the top electrode layer, and a conductive metal bit line (150) in contact with the metal silicide layer opposite from the metal silicon nitride layer.

Abstract: Techniques related to generating holographic images are discussed. Such techniques include application of a pre-trained deep neural network to a target holographic image to generate a feedback strength value for error feedback in an iterative propagation feedback model and generating a diffraction pattern image corresponding to the target holographic image by applying the iterative propagation feedback model based on the target holographic image and using the feedback strength value.

Abstract: Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for forming III-N transistor structures that include a graded channel region. The disclosed transistors may be implemented with various III-N materials, such as gallium nitride (GaN) and the channel region may be graded with a gradient material that is a different III-N compound, such as indium gallium nitride (InGaN), in some embodiments. The grading of the channel region may provide, in some cases, a built in polarization field that may accelerate carriers travelling between the source and drain, thereby reducing transit time. In various embodiments where GaN is used as the semiconductor material for the transistor, the GaN may be epitaxially grown to expose either the c-plane or the m-plane of the crystal structure, which may further contribute to the built-in polarization field produced by the graded channel.

Abstract: An example apparatus for encoding video frames includes a receiver to receive a current frame to be encoded, and a quantization parameter and statistics for the current frame. The apparatus also includes a frame motion analyzer to detect a motion activity status for the current frame based on the statistics via a motion activity analysis. The apparatus further includes a motion adaptive frame inserter to adaptively switch between a regular reference list management and a long-term reference frame insertion based on the detected motion activity status and the quantization parameter. The apparatus also further includes an encoder to encode the current frame using the regular reference list management or the long-term reference frame insertion.