Abstract: In embodiments, apparatuses, methods, and storage media may be described for identifying a quick response (QR) image. A QR control code (QRCC) may be identified in the QR image based on a QR tag in the image. Based on the QRCC, a control command of an apparatus may be identified. Other embodiments may be described and/or claimed.

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to facilitate electronic data security. An example apparatus includes a data storage including a memory adjusted to store data organized according to a data table including columns identifying a first data record and a first security tag associated with the first data record. In the example apparatus, retrieval of data from the data storage involves a bit operation comparing the first security tag with a first privilege tag. In the example apparatus, the data storage provides the first data record when the bit operation comparing the first security tag with the first privilege tag has a non-zero result, and the data storage does not provide the first data record when the bit operation comparing the first security tag with the first privilege tag has a zero result.

Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

Abstract: Technologies for network communication using pooled memory include a computing rack having a pooled memory enclosure with a pooled memory controller and a compute enclosure having two or more compute nodes. A first compute node determines a destination virtual network interface controller identifier (vNIC ID) associated with a destination network address. The first compute node transmits a send message to the pooled memory controller that includes the destination vNIC ID and a sender physical address of packet data within the pooled memory. The pooled memory controller transmits a receive message to a second compute node associated with the destination vNIC ID. The second compute node transmits a receiver physical address of a receive buffer within the pooled memory to the pooled memory controller. The pooled memory controller copies the packet data from the sender physical address to the receiver physical address. Other embodiments are described and claimed.

Abstract: Examples may include a determining a checkpointing/delivery policy for primary and secondary virtual machines based on output-packet-similarities. The output-packet-similarities may be based on a comparison of time intervals via which content matched for packets outputted from the primary and secondary virtual machines. A checkpointing/delivery mode may then be selected based, at least in part, on the determined checkpointing/delivery policy.

Abstract: In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.

Abstract: A technique allows for a hybrid hypervisor-assisted security model that monitors and protects an operating system from rootkits or other malware through use of monitoring policies for the operating system (OS). The OS monitoring policies may be separated into rules that can be enforced using an in-guest agent running in a monitored guest OS domain and an out-of-guest agent running in a privileged/monitoring guest OS domain. Embodiments may use virtualization technologies including permissions and policies in one or more page tables (and virtualization exceptions (# VE) to avoid virtual machine (VM) exits during runtime events and thereby, avoid context switching into a hypervisor. An embodiment includes configuring the in-guest agent in a monitored OS such that hardware events can be switched to lightweight events and can be dynamically switched to complex processing in the privileged OS domain only when requested.

Abstract: Embodiments are generally directed to a multi-phase architecture for multiple rate pixel shading. An embodiment of an apparatus includes one or more processor cores, the one or more processing cores including a graphics pipeline and a memory to store data for graphics processing, the data including pixel data. The graphics pipeline includes a multi-phase shader for processing of pixel data, the multi-phase shader including multiple rendering stages, the rendering stages including at least a first stage for a first granularity and a second stage for a second, different granularity, the second rendering granularity being a finer granularity than the first rendering granularity. The multi-phase shader is structured to provide a hierarchy for image rendering, wherein pixel data is received at a rendering stage having a coarsest rendering granularity, with remaining pixel data being provided through the hierarchy to one or more rendering stages having finer rendering granularities.

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

Abstract: Systems and methods may provide for online identification and authentication. In one example, the method may include generating a credential to represent a relationship based on a common ground of authenticated communication between a first user and a second user, identifying the second user to the first user, authenticating the relationship of the second user to the first user, and initiating, upon authentication, a communication between the first user and the second user.

Abstract: Embodiments of a Next Generation Node-B (gNB) and User Equipment (UE) are generally described herein. The gNB may transmit control signaling to configure transmission of position reference signals (PRSs) by a plurality of transmit-receive points (TRPs). The gNB may receive, from the UE, for each of the TRPs, a set of signal location parameters (SLPs). The gNB may perform an iterative process to estimate a position of the UE. For a current iteration, the gNB may: determine a current estimate of the position of the UE based on a current plurality of sets of SLPs; and determine a cost function for each of the current plurality of sets of SLPs. The gNB may determine, based on the cost functions, a next plurality of sets of SLPs for a next estimate of the position of the UE.

Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract: The techniques disclosed herein include a computing device for Internet of Things (IoT) solution sizing. The computing device is to determine a solution deployment metric, trigger edge traffic, monitor a round trip characteristic and an actuation pattern, execute permutations of input workloads, and determine a solution deployment.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.

Abstract: Provided are a computer product, method, and system to generate a virtual subsystem to process read and write requests to storage devices. A virtual subsystem is configured in the memory to provide a representation of a subsystem presented to at least one host system. The at least one host system is to communicate with the virtual subsystem to access the at least one storage device. At least one virtual namespace is configured in the memory for the virtual subsystem. Each of the at least one virtual namespace maps to at least one physical namespace in at least one storage device. Each virtual namespace is assigned to one host system to use to direct read and write requests to the at least one physical namespace of the at least one storage device assigned to the virtual namespace.