Abstract: An apparatus and method for hybrid rendering. For example, one embodiment of a method comprises: identifying left and right views of a user's eyes; generating at least one depth map for the left and right views; calculating depth clamping thresholds including a minimum depth value and a maximum depth value; transforming the depth map in accordance with the minimum depth value and maximum depth value; and performing view synthesis to render left and right views using the transformed depth map.

Abstract: Various mechanisms for implementing power activation of electronic tags via conductive contact labels are provided herein. An electronic shipping tag includes a housing to enclose: a printed circuit board having: a battery; load circuitry; and a plurality of pins that project from the housing, such that when contacted with a conductive substrate, cause activation of the load circuitry.

Abstract: Devices and systems having memory-side adaptive prefetch decision-making, including associated methods, are disclosed and described. Adaptive information can be provided to memory-side controller and prefetch components that allow such memory-side components to prefetch data in a manner that is adaptive with respect to a particular read memory request or to a thread performing read memory requests.

Abstract: In various embodiments, a biometric rating system (“BRS”) may generate ratings based on biometric data. The BRS may receive biometric data, along with location data, from personal devices of a user. The BRS may identify a location at which the biometric data was measured. The BRS may generate one or more ratings associated with the location, such as ratings for a venue or event at the location. The BRS may also perform calibration of the biometric data. For example, the BRS may be configured to partition biometric data measurements into multiple segments to be associated with different locations, different areas at a location, or different portions of an event. The BRS may calibrate biometric data based on activity or social media or proximity data. The BRS may generate a rating based on the calibrated biometric data. Other embodiments may be described and/or claimed.

Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.

Abstract: Technologies for managing event notifications on an interface of a display of a destination computing device include a plurality of source computing devices wirelessly coupled to the destination computing device via digital content communication channels usable to receive digital content streams from each of the source computing devices and event communication channels usable to receive one or more event notifications from one or more of the source computing devices. The destination computing device is configured to output the received event notifications to an interface of the display to a user, as well as any graphical user interface (GUI) control elements associated with actionable responses of the received event notifications. The destination computing device is further configured to detect selection of the GUI control elements and initiate a response/action associated with a selected GUI control element. Other embodiments are described and claimed herein.

Abstract: Embodiments are generally directed to switchable input modes for external display operation. An embodiment of an electronic device includes a touchscreen display; a processor; a connection for an external monitor; and a switch button. The electronic device includes a switchable input state including a first input mode for which the touchscreen display operates as a touchscreen input and a second input mode for which the touchscreen display operates as an input device for the operation of the external monitor, and the processor is to change operation of the electronic device to the first input mode or to the second input mode based upon a selection of input mode received from a user using the switch button.

Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.

Abstract: Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method are described for performing virtualization using virtual machine (VM) sets. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; a hypervisor to virtualize the GPU to share the GPU among a plurality of virtual machines (VMs); and VM set management logic to establish a plurality of VM sets, each set comprising a plurality of VMs, the VM set management logic to partition graphics memory address (GMADR) space across each of the VM sets but to share the GMADR space between VMs within each VM set.

Abstract: Embodiments of the present disclosure may relate to a data storage controller that may include a host interface to receive a request from a host to perform a data copy operation on a non-volatile data storage component of a data storage device, where the request identifies one or more source ranges of the non-volatile data storage component from which data is to be copied, a destination range of the non-volatile data storage component to which the data is to be copied, and a transfer length in bytes for each of the one or more source ranges, and a processor coupled with the host interface to process the request from the host to perform the data copy operation to copy the data from the one or more source ranges to the destination range based at least in part on the transfer length in bytes. Other embodiments may be described and/or claimed.

Abstract: A method and apparatus for monitoring operational parameters in an IoT device is provided. An exemplary method includes performing a statistical analysis of a system metric. A determination is made as to whether an alert limit has been breached. If so, a message is constructed and dispatched to a server.

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described. In one example, compression in graphics rendering may include determining a plurality of color values associated with individual pixels of a tile of pixels, generating a subset of the plurality of color values such that the subset of the plurality of color values include one or more distinct color values from the plurality of color values, associating an index value with each color value of the subset of the plurality of color values, determining, for each of the individual pixels, an associated pixel index value to generate a plurality of pixel index value associated with the individual pixels of the tile of pixels, storing, in memory, graphics data including the subset of the plurality of color values, the associated index values, and the plurality of pixel values.

Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

Abstract: An apparatus, method and machine-readable storage medium to improve memory access performance between shared local memory and system global memory are described. The method comprises grouping two or more work groups to form a super workgroup, and positioning a portion of a memory space into one or more super shared local memories (Super SLMs), wherein the memory space which is shared within the super workgroup forms at least one Super SLM of the one or more Super SLMs. The apparatus comprises: a plurality of execution units; a cache memory having a portion which operates as a shared local memory (SLM), which is shared with the plurality of execution units, at least one of which operates on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units operates on the different work groups.

Abstract: An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.

Abstract: Systems, methods, and circuitries for regulating voltage supplied to a power amplifier are disclosed. In one example, a buck-boost control system is configured to control a buck-boost converter to operate in either a buck mode or a boost mode. The system includes compensator circuitry configured to determine a target current based on a difference between a target voltage and a regulated output voltage of the buck-boost converter and determine a tolerance current that, with the target current, defines a range of expected coil current for the present operating mode. Based on the difference between the target voltage and the regulated output voltage, a charge control signal or a discharge control signal is generated for the converter to cause the coil current to approach the target current. Mode control circuitry is configured to switch the buck-boost converter to the other operating mode when the coil current reaches the tolerance current.

Abstract: Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.

Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.