Patents Assigned to Intel Corporations
  • Dynamic memory for compute resources in a data center
    Patent number: 10616669
    Abstract: Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into first level and second level memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory resources. The first set of physical memory resources can be coupled to the physical compute resources via a local interface while the second set of physical memory resources can be coupled to the physical compute resources via a fabric.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Temperature sensing based flow monitoring and fault detection
    Patent number: 10612980
    Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
  • Adaptive internet of things edge device security
    Patent number: 10616249
    Abstract: In an example, there is disclosed an apparatus, including: a network interface to communicatively couple to an internet of thing (IoT) having at least one edge device; a gateway engine to provide gateway services to one or more edge devices via the network interface; and one or more logic devices, including at least one hardware logic device, providing an adaptive security engine to: compile a periodic device interaction summary (DIS) for the edge device; send the DIS to a cloud service; receive from the cloud service a DIS signature for the edge device; determine that one or more interactions from the edge device are suspicious; and act on the determining.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Subramanian C, Balachandar Santhanam
  • Apparatus, system and method of communicating a transmission according to a symbol block structure and guard interval (GI) scheme
    Patent number: 10615930
    Abstract: Some demonstrative embodiments include apparatus, system and method of communicating a transmission according to a symbol block structure and Guard Interval (GI) scheme. For example, an apparatus may include logic and circuitry configured to cause a wireless station to generate a plurality of Single Carrier (SC) blocks according to a SC block structure corresponding to a GI type of a plurality of GI types, a SC block of the plurality of SC blocks including a GI followed by a data block, the GI including a Golay sequence having a length based at least on the GI type, a length of the data block is based at least on the GI type; and to transmit a SC transmission over a millimeter Wave (mmWave) frequency band based on the plurality of SC blocks.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Artyom Lomayev, Iaroslav P. Gagiev, Alexander Maltsev, Michael Genossar, Carlos Cordeiro
  • Wireless component state based power management
    Patent number: 10613606
    Abstract: Apparatuses, methods and storage medium associated with power management, are disclosed herein. In embodiments, an apparatus for computing may include one or more processors, with each processor having one or more processor cores; one or more wireless communication components; memory coupled with the one or more processors to host a plurality of virtual machines operated by the one or more processors; and a virtual machine monitor to be loaded into the memory and operated by the one or more processors to manage resource allocation to the virtual machines. The virtual machine monitor may include a power manager to manage power consumption of the apparatus, based at least in part on states of the wireless communication components. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventor: Alexander W. Min
  • Method and system of camera control and image processing with a multi-frame-based window for image data statistics
    Patent number: 10616511
    Abstract: A method, system, and article is directed to camera control and image processing with a multi-frame-based window for image data statistics.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Liron Ain-Kedem, Jarno Nikkanen
  • Architecture and instruction set for implementing advanced encryption standard (AES)
    Patent number: 10615963
    Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal
  • Technologies for managing resource allocation with phase residency data
    Patent number: 10616668
    Abstract: Technologies for allocating resources of a set of managed nodes to workloads based on resource utilization phase residencies include an orchestrator server to receive resource allocation objective data and determine an assignment of a set of workloads among the managed nodes. The orchestrator server is further to receive telemetry data from the managed nodes, determine, as a function of the telemetry data, phase residency data, determine, as a function of at least the phase residency data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing the achievement of any of the other resource allocation objectives, and apply the adjustment to the assignments of the workloads among the managed nodes as the workloads are performed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Susanne M. Balle, Rahul Khanna, Nishi Ahuja, Mrittika Ganguli
  • Device and method for scheduling an allocation of a set of link resources
    Patent number: 10615943
    Abstract: A scheduling device for scheduling an allocation of a set of link resources includes: a prediction circuit configured to generate a predicted link quality for a first link resource of the set of link resources; a classification circuit configured to classify the first link resource to a classification pattern based on the predicted link quality of the first link resource; and an allocation circuit configured to allocate the first link resource to a first transmission or retransmission subframe set based on the classification pattern.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Holger Neuhaus, Xiaofeng Wu, Bertram Gunzelmann, Axel Huebner
  • Programmable IMON accuracy in power systems
    Patent number: 10613618
    Abstract: To compensate for inaccuracies in reported values for current output from a voltage regulator (VR) to a processor, the VR may be tested, and a load line determined so the processor can calculate the inaccuracy. This load line may be programmed into the BIOS as an offset, and the BIOS values used from then on so the CPU can determine what the true inaccuracy is, as opposed to the inaccuracy requested of the VR manufacturer. These values may be used during operation to control CPU turbo mode and CPU throttling.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Tawfik Rahal-Arabi, Mo S. Bashir
  • Die package with superposer substrate for passive components
    Patent number: 10615133
    Abstract: A die package is described that includes a substrate to carry passive components. In one example, the package has a semiconductor die having active circuitry near a front side of the die and having a back side opposite the front side, and a component substrate near the back side of the die. A plurality of passive electrical components are on the component substrate and a conductive path connects a passive component to the active circuitry. The die has a silicon substrate between the front side and the back side and the conductive path is a through-silicon via through the die from the back side to the active circuit.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Valluri R. Rao
  • Device, system and method to access a shared memory with field-programmable gate array circuitry without first storing data to computer node
    Patent number: 10613999
    Abstract: Techniques and mechanisms for providing a shared memory which spans an interconnect fabric coupled between compute nodes. In an embodiment, a field-programmable gate array (FPGA) of a first compute node requests access to a memory resource of another compute node, where the memory resource is registered as part of the shared memory. In a response to the request, the first FPGA receives data from a fabric interface which couples the first compute node to an interconnect fabric. Circuitry of the first FPGA performs an operation, based on the data, independent of any requirement that the data first be stored to a shared memory location which is at the first compute node. In another embodiment, the fabric interface includes a cache agent to provide cache data and to provide cache coherency with one or more other compute nodes.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Daniel Rivas Barragan, Patrick Lu
  • Multi-modal real-time camera localization and environment mapping
    Patent number: 10616552
    Abstract: Methods, apparatuses and systems may provide for conducting a quality assessment of a depth localization mode, a color localization mode and an inertia localization mode, and selecting one of the depth localization mode, the color localization mode or the inertia localization mode as an active localization mode based on the quality assessment. Additionally, a pose of a camera may be determined relative to a three-dimensional (3D) environment in accordance with the active localization mode.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Daniel J. Mirota, Samer S. Barakat, Haowei Liu, Duc Q. Pham, Mohamed Selim Ben Himane
  • Printed circuit board (PCB) with three-dimensional interconnects to other printed circuit boards
    Patent number: 10617000
    Abstract: A system for a three-dimensional (“3D”) printed circuit board (“PCB”) to printed circuit board interface is provided. A first PCB includes first landing pads disposed on one or more edges of the first PCB. The first landing pads electrically couple to conductive pins or second landing pads disposed on a second PCB. The second landing pads may be disposed in a slot in the second PCB. The interface between the first landing pads and the second landing pads may provide various advantages over traditional PCB to PCB interfaces, such as, improved signal integrity, improved power integrity, increased contact density, decreased clock jitter, etc.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Daqiao Du, Zhen Zhou, Jun Liao, James A. McCall, Xiang Li, Kai Xiao, Zhichao Zhang
  • Methods and apparatus to establish a connection between a supplicant and a secured network
    Patent number: 10613994
    Abstract: Methods, apparatus, systems and articles of manufacture to establish a connection between a supplicant and a secured network are disclosed. An example method includes relaying, by executing an instruction with a processor, a first request for access to a secured network received from a supplicant to an authentication server. An identifier provided by the supplicant is stored in a memory. In response to detection of the processor resuming operation from a failure event, a second request for access to the secured network to the authentication server is transmitted on behalf of the supplicant, the second request including the identifier provided by the supplicant stored in the memory.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 7, 2020
    Assignee: INTEL CORPORATION
    Inventor: Prahbu Somasandharam
  • Systems and methods for electromagnetic interference shielding
    Patent number: 10615128
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Method and system to provide user-level multithreading
    Patent number: 10613858
    Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Edward Grochowski, Hong Wang, John P. Shen, Perry H. Wang, Jamison D. Collins, James Held, Partha Kundu, Raya Leviathan, Tin-Fook Ngai
  • Dynamically controlling cache size to maximize energy efficiency
    Patent number: 10613614
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Stacked light wave guides for display panels
    Patent number: 10613269
    Abstract: Disclosed herein is a waveguide stack and associated segmented illumination display. The waveguide stack includes a number of waveguides stacked into an array to direct light from light emitting diode (LED) edge lights to a liquid crystal display (LCD) of a segmented illumination display. The waveguides are stacked with light inhibiting material between the waveguides to inhibit light transmitting through one waveguide from communicating to a second waveguide.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 7, 2020
    Assignee: INTEL CORPORATION
    Inventors: Duncan Glendinning, Roland P. Wooster, Zhiming J. Zhuang
  • Dynamic configuration of caches in a multi-context supported graphics processor
    Patent number: 10613972
    Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including an on-die cache and a cache configuration circuitry to dynamically configure the on-die cache for a plurality of contexts executed by the GPU. The cache configuration block is to receive a cache configuration request, the cache configuration request including context-specific cache requirements for a new context, and determine a priority associated with the context-specific cache requirements. The CCB can compare the context-specific cache requirements with pre-existing cache requirements based on the priority, and reallocate the cache based on the context-specific cache requirements and the priority.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Balaji Vembu, Pattabhiraman K, Altug Koker