Abstract: A push-pull amplifier includes an amplifier input, a push amplifier stage, a pull amplifier stage and an inverting amplifier output.

Abstract: A method includes receiving a signal comprising a symbol-carrier matrix, the symbol-carrier matrix including a predetermined pattern of reference symbols, and determining at least one channel estimate ?i,k at at least one of the reference symbol positions of the reference symbols in the symbol-carrier matrix, wherein i=0,1,2, . . . is the carrier index and k=0,1,2, . . . is the symbol index of the symbol-carrier matrix. The method further includes determining a Doppler spread {circumflex over (?)}D on the basis of the at least one channel estimate ?i,k.

Abstract: The present disclosure relates to a device and method to increase the dynamic bit range of a radio-frequency digital-to-analog converter. A load of the Cap-RF-DAC typically consists of a transformer, which has a transfer ratio N:M derived by the number of windings of the primary and secondary coil, respectively. The load resistance can be varied by using switchable inductors on one or both sides of the transformer to vary an inductance of one of more sides of the switchable transformer, varying the transfer ratio of a transformer resulting in a switchable trans-impedance gain of the transformer. Switchable capacitor may also be configured in parallel to the switchable transformer to keep the load impedance constant while switching the switchable transformer.

Abstract: A method, system, and apparatus for managing a plurality of cipher processor units. A cipher module may receive a cipher instruction indicating a cipher algorithm to be used. The cipher module may identify a cipher processing unit of the plurality of cipher processing units associated with the cipher algorithm. The cipher module may execute the cipher instruction using the cipher processing unit and the common register array. The cipher module may store a state of a common register array to be used by the cipher processing unit of the plurality of cipher processing units.

Abstract: A loop filter includes an input terminal, an output terminal, and a control terminal for a selection signal. At least one low pass filter is disposed between that input terminal and that output terminal. The loop filter is adapted to select a configuration out of a first configuration and at least one second configuration in response to the selection signal. In the first configuration, the loop filter comprises a non-integrating transfer characteristic in operation. In the second configuration, the loop filter comprises an integrating signal transfer characteristic in operation.

Abstract: Various embodiments of a wireless multimode receiver having an off-chip duplex filter associated with a multimode band, and a blocker cancellation circuit disposed on a semiconductor chip are described in the present disclosure.

Abstract: A frequency divider arrangement for providing a quadrature output signal with a quadrature output signal frequency, includes a signal source for providing a base signal with a base signal frequency at the output side. Further, the frequency divider arrangement includes a first integer number quadrature divider with a first divider ratio for receiving the base signal on the input side and for providing a first quadrature signal with a first quadrature signal frequency according to the first divider ratio of the first integer number quadrature divider.

Abstract: A communication device is provided comprising a message generator configured to generate a message indicating that a mobile terminal should provide data from which information about the configuration of the mobile terminal for the reception of paging messages is derivable and a transmitter configured to transmit the message.

Abstract: A device such as a worker, window-size and iteration control unit (WWICU) is proposed. The WWICU determines processing, iteration, and window information based on format information indicative of one or more formats to be processed by a decoding process. The processing information may include a number of parallel workers, the iteration information may include a number of half-iterations, and the window information may include a window size to be used in the decoding process. The WWICU then determines time information including a total cycle count based on the processing information, the iteration information, and the window information. In response to determining that the total cycle count is not beyond a threshold value, the WWICU may transmit configuration information including the processing, iteration, and window information to a device, such as a turbo decoding device, configurable to perform the decoding process based on the configuration information.

Abstract: A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.

Abstract: A method for operating a transceiver circuit includes receiving an information indicating at least one of a transmission and a reception in a guard band region of a frequency band supported by a communications network and allocating at least a part of the guard band region of the supported frequency band of the communications network for at least one of a transmission and a reception of at least one physical channel.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.

Abstract: A server may be provided. The server may include: an association circuit configured to associate with a first address according to a first address scheme according to a communication control protocol, by which a communication device may be addressed, a second address according to a second address scheme, by which the communication device may not be addressed.

Abstract: A method of estimating interference and noise of a communications channel includes receiving a data sequence transmitted over the communications channel at a receiver, and computing a sequence of channel estimates based on the received data sequence. The method also includes computing a difference sequence based on the sequence of channel estimates and the sequence of channel estimates subjected to a displacement in time or frequency, and determining a covariance measure of the difference sequence as an estimate of the interference and noise of the communications channel.

Abstract: A method includes receiving a signal transmitted by a transmitter, wherein the transmitter transmits with a transmit power and the signal includes a pilot signal transmitted by the transmitter with a fraction of the transmit power. The method further includes equalizing the received signal, determining a despread pilot signal based on the equalized signal, and determining the fraction of the transmit power based on the despread pilot signal.

Abstract: The disclosed invention relates to an antenna configuration that is configured to tune the frequency of transmission without using filters. The antenna configuration comprises a tunable multi-feed antenna configured to wirelessly transmit electromagnetic radiation. A signal generator is configured to generate a plurality of signals that collectively correspond to a signal to be transmitted. The plurality of signals have a phase shift or amplitude difference therebetween. The plurality of signals are provided to a plurality of antenna feeds connected to different spatial locations of the tunable multi-feed antenna. The values of the phase shift and/or amplitude difference define an antenna reflection coefficient that controls the frequency characteristics that the tunable multi-feed antenna operates at, such that by varying the phase shift and or amplitude difference, the frequency characteristics can be selectively adjusted.

Abstract: This disclosure relates to linearization in polar modulators of wireless communication devices, to attain linear amplification and high power efficiency during transmission.

Abstract: A method includes receiving a signal via a channel, determining a feedback information based on the received signal, and determining a quality indicator based on the feedback information, wherein the quality indicator indicates a quality of the received signal. The method further includes starting or resuming a transmission of the feedback information if the quality indicator fulfills a predetermined condition.

Abstract: For example, a communication device may be provided comprising an oscillator configured to generate a reference signal; an accuracy determiner configured to determine information about an accuracy of a frequency of the reference signal; a signal detector configured to detect the presence of a radio signal; and a controller configured to control the signal detector based on the information.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.