Abstract: This disclosure relates to a continuous open loop control to closed loop control transition.

Abstract: An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain term

Abstract: An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain term

Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.

Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Abstract: A communication device is described including a transceiver configured to establish a communication channel via a first radio cell and receive idle mode information of a second radio cell via the communication channel.

Abstract: A noise reduction device may be provided. The noise reduction device may include: an input configured to receive an input signal including a representation in a frequency domain of an audio signal, wherein the representation includes a plurality of time frames and a plurality of coefficients for each time frame; a noise detection circuit configured to determine a first indicator being indicative of a bandwidth of a coefficient over at least two time; a noise reduction circuit configured to reduce based on the first indicator a noise component in the audio signal; and an output configured to output an output signal including a representation in the frequency domain of the audio signal with the reduced noise component.

Abstract: A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

Abstract: A radio receiver apparatus of a cellular network includes a channel estimator configured to calculate channel estimates on the basis of a common pilot channel. The apparatus further includes a weight calculation unit configured to calculate a weighting factor on the basis of a signal power of the common pilot channel and control data depending on a transmit signal power of a dedicated data channel. The control data is signaled by the cellular network to the radio receiver apparatus. The radio receiver apparatus further comprises a combiner that combines the signals from multiple cells by using the channel estimates and the weighting factor.

Abstract: The method includes receiving a data signal, the data signal including two training sequences, performing a first evaluation of the data signal based on a first training sequence of the two training sequences, performing a second evaluation of the data signal based on a second training sequence of the two training sequences, and processing the data signal based on a result of the first and second evaluations.

Abstract: A method for transmitting data between a radio transmitting device and a radio receiving device includes transmitting a frame structure over a radio channel, the frame structure including a control channel and a data channel. The method further includes detecting a quality degradation of the radio channel, selecting a bit from the data channel and increasing a transmission power of the selected bit when the quality degradation of the radio channel is detected.

Abstract: An apparatus for determining a target precoding matrix from a plurality of precoding matrix candidates is provided. The apparatus includes a covariance matrix value provider, a real part determiner and a precoding matrix determiner. The precoding matrix determiner is adapted to determine the target precoding matrix from the plurality of precoding matrix candidates, wherein the precoding matrix determiner is configured to determine the target precoding matrix based on at least one of the one or more real covariance values.

Abstract: A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus; and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

Abstract: The present invention relates to a method and system for communication in a mobile device. First and second OFDM symbols containing first and second received cell-specific reference subcarriers, respectively, are received. First and second received cell-specific reference subcarriers of the first and second OFDM symbols are extracted. A pair of received subcarriers is generated by computing the scalar product of the first received cell-specific reference subcarrier and the conjugate of the second received cell-specific reference subcarrier. A reference sequence is provided, that contains pairs of reference subcarriers for multiple, possible combinations of cell-IDs. The pair of received subcarriers is correlated with each pair of reference subcarriers of the reference sequence to generate cell-specific correlation values associated with each cell-ID of a plurality of cell-specific correlation values. The cell-ID of the strongest cell is determined by searching for the highest correlation value.

Abstract: A communication terminal is described comprising a transmitter configured to generate a transmit signal and a measurement circuit configured to receive the generated transmit signal and to measure the power of the received transmit signal in a predetermined frequency region.

Abstract: Method for synchronizing a plurality of mobile radio devices, mobile radio devices and a method for synchronizing a mobile radio device. In one embodiment of the invention, a method for synchronizing a plurality of mobile radio devices is provided including transmitting a downlink synchronization signal in a shared downlink synchronization channel to a plurality of mobile radio devices, and receiving a plurality of uplink synchronization signals via a plurality of dedicated uplink synchronization channels.

Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.

Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract: A signal delay estimator includes an adjustable delay element for delaying a first signal to obtain a delayed first signal, a delay amount estimator for estimating a delay amount between the delayed first signal and a second signal that is similar and delayed relative to the first signal, and a leading signal determiner for determining whether the delayed first signal leads the second signal or vice versa, and for generating a corresponding binary signal. A selective inverter is provided for selectively inverting the delay amount depending on the binary signal. The signal delay estimator also includes a feedback element to the adjustable delay element for controlling a delay based on an output of the selective inverter. Another exemplary signal delay estimator includes a closed control loop with an adjustable delay element and separate first and second processing paths for absolute delay amount and delay direction, respectively.