Abstract: A trace monitor configured to trace an exchange of a plurality of signals between a master device and a slave device of the system on chip, wherein the plurality of signals have a number of requests and a number of responses; and track the number of requests and the number of responses made before and after tracing is activated to determine which Reponses of the number of responses to trace after tracing is activated and a remaining number of responses to trace after tracing is deactivated.

Abstract: Embodiments of the invention relate generally to radio communication devices and to a method for controlling frequency selection. In an embodiment of the invention, a radio communication device is provided. The radio communication device may include a first medium access control unit, a second medium access control unit, a common scheduling unit configured to control the first medium access control unit and the second medium access control unit, and a communication interface configured for frequency selection communication between the first medium access control unit and the second medium access control unit, wherein at least one frequency channel to be used is exchanged between the first medium access control unit and the second medium access control unit.

Abstract: A device a radio communication device may be provided. The radio communication device may include: an antenna configured to operate in a plurality of operation modes; a receiver configured to receive a first channel signal and a second channel signal using the antenna; and a mode switching circuit configured to switch an operation mode of the antenna if the first channel signal fulfils a first channel specific criterion or configured to switch an operation mode of the antenna if the second channel signal fulfils a second channel specific criterion.

Abstract: According to an aspect of this disclosure, a communication device is provided comprising a first interface configured to receive a first packet supplied by a packet encoder; a determiner configured to determine a time difference between the time at which the first packet is ready to be sent by the communication device and a time at which communication resources for sending the first packet are available; a generator configured to generate information from which it is derivable when a second packet should be provided by the packet encoder based on the time difference; and a second interface configured to transmit the information to the packet encoder.

Abstract: An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined period of time, a hardware comparator to compare a number of write accesses counted by the hardware counter with at least one predetermined threshold value, the hardware comparator further to generate a control signal, the control signal being dependent on a result of a comparison of a number of write accesses counted by the hardware counter with at least one predetermined threshold value performed by the hardware comparator, and a clock frequency setting circuit to set a clock frequency of a processor depending on the control signal.

Abstract: A receiver includes a first amplifier and a second amplifier, a first mixer, a second mixer and a third mixer, a first baseband signal path and a second baseband signal path. A signal output of the first amplifier is coupled to a signal input of the first mixer and a signal input of the second mixer. A signal output of the second amplifier is coupled to a signal input of the third mixer. A signal output of the first mixer and a signal output of the third mixer are coupled to the first baseband signal path. A signal output of the second mixer is coupled to the second baseband signal path.

Abstract: An amplifier circuit includes a gain controller, a first amplifier, and a second amplifier which is coupled in series to the first amplifier, the second amplifier comprising a plurality of amplifying units.

Abstract: A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device.

Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.

Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.

Abstract: A method includes receiving a signal including a co-channel interference, channel equalizing the received signal and processing the channel equalized signal based on a first precoding vector such that the co-channel interference is mitigated.

Abstract: A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel.

Abstract: A detector for zero crossings and a counter which is connected to it are used to determine the time intervals between the zero crossings of the received signal or of an intermediate-frequency signal which is produced from the received signal, and for detection of the digital signal data. In this case, a sequence of determined zero crossing intervals can be stored in digital form in a shift register chain, and can be compared in a classification device with previously stored interval sequences. Furthermore, a frequency offset can be determined by averaging the zero crossing intervals and can be compensated for by suitable selection or modification of the previously stored interval sequences, in which case the latter can also be used during the synchronization phase. The synchronization process may, furthermore, be assisted by payload data identification.

Abstract: This disclosure relates to linearization in polar modulators of wireless communication devices and associated methods, to attain linear amplification and high power efficiency during transmission.

Abstract: According to various aspects of this disclosure, a circuit arrangement is provided. The circuit arrangement may include: a memory configured to store a first encryption key for generating a first authentication vector for authentication between a mobile station and a home network of the mobile station; and a key-generator configured to derive a second encryption key from the first encryption key, the second encryption key for generating a second authentication vector for authentication between the mobile station and a visited network.

Abstract: The method includes receiving a data signal, the data signal including two training sequences, performing a first evaluation of the data signal based on a first training sequence of the two training sequences, performing a second evaluation of the data signal based on a second training sequence of the two training sequences, and processing the data signal based on a result of the first and second evaluations.

Abstract: A receiver apparatus includes a first receiver having an input for receiving a first version of a signal received by a first receive antenna. The receiver apparatus further includes a second receiver having an input for receiving a second version of the same signal received by a second receive antenna. The first receiver includes a first constellation demapper for demapping constellation symbols generated in the first receiver into a first soft decision bitstream and the second receiver includes a second constellation demapper for demapping constellation symbols generated in the second receiver into a second soft decision bitstream. A combiner is configured to combine the first soft decision bitstream and the second soft decision bitstream to provide a combined soft decision bitstream.

Abstract: A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

Abstract: In an embodiment, a mobile radio communication device is provided. The mobile radio communication device may include a mobile radio communication protocol circuit configured to provide a home base station function for a mobile radio communication with another mobile radio communication device, and a memory configured to store a home base station group data structure, wherein the home base station group data structure for each communication device associated with the home base station group comprises a home base station group member identifier to identify a mobile radio communication device as a member of the home base station group.

Abstract: A switched mode power supply includes a first switch connected to an input terminal for inputting an input voltage, a second switch, an inductor and an output capacitor, a transformer connected to the first switch, and a pulse generator connected to the switch.