DRAIN EXTENDED MOS DEVICE FOR BULK FINFET TECHNOLOGY
Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.
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A conventional planar complementary metal oxide semiconductor (CMOS) transistor has four parts: a source, a drain, a channel disposed between the source and drain, and a gate disposed over the channel to control the channel. In planar CMOS transistors, the source, drain, and channel are formed by implanting ions into a planar semiconductor substrate, and the gate is then formed over a surface of the semiconductor substrate so as to overlie the channel. Engineers continuously seek to shrink the size of such transistors over successive generations of technology to “pack” more transistors into a given unit area, which provides consumers with devices that exhibit improved functionality.
One of the more recent advances in this continuing effort to shrink the size of CMOS transistors is the advent of fin field effect transistors (FinFETs). Unlike planar CMOS transistors where the source, drain, and channel are formed in a planar substrate; in FinFETs the source, drain, and channel region are formed in a thin slice of semiconductor material (i.e., a “fin”), which extends upward from the semiconductor substrate. A gate is then formed over the channel region in the fin. During operation, the gate is turned on to put the channel in a highly conductive state that allows electrons or holes to easily move from source to the drain. Conversely, when the gate is switched off, this conductive path in the channel region is supposed to disappear. Although this basic functionality is well established, unfortunately, it has been difficult to efficiently manufacture FinFETs that reliably withstand large voltages for high voltage and input/output circuit operations. Therefore, the present disclosure provides improved techniques for high-voltage FinFETs.
The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. Further, to the extent that some illustrated aspects may be described with reference to a Fin field effect transistor (FinFET), it will be appreciated that the term FinFET includes, but is not limited to: tri-gate transistors, omega transistors, multi-gate transistors (MUGFETs) and the like, all of which are contemplated as falling within the scope of the present disclosure.
Whereas conventional techniques have struggled with how to efficiently manufacture FinFETs to reliably withstand large voltages, the present disclosure relates to improved techniques for drain extended high voltage FinFETs. In particular, some aspects of the present disclosure form a drain extension region in a lower portion of a semiconductor fin between a gate electrode and a drain region of a high-voltage FinFET. To streamline manufacture of this high voltage (e.g., drain extended) FinFET and ensure it integrates well with low-voltage FinFETs, the drain extension region can be formed by using a punch-through implant used to concurrently form low-voltage FINFETs. Thus, this punch-through implant forms a punch-through blocking region for the low-voltage FinFETs. Consequently, the present disclosure reuses an existing implant (e.g., a punch-through implant) for a new configuration that improves manufacturing efficiency.
During operation, a voltage bias is applied between the conductive gate electrode 112 and source 106 (so called VGS bias). When VGS is greater than a threshold voltage (VT) of the FinFET 100, the channel region 114 is put in a highly conductive state that allows electrons or holes to easily move from source 106 to drain 108 in the presence of a voltage between source and drain (VDS). Conversely, when VGS is less than VT, the channel region 114 is in a high impedance state so little or no carriers flow between source 106 and drain 108. Notably, even when the channel region 114 is in the high impedance state, but for the punch-through blocking region 118, excess carriers could “leak” from source 106 to drain 108—particularly deeper in the fin 102 beneath the channel region 114 where the gate electrode 112 is less able to control the potential applied. Because the punch-through blocking region 118 has a conductivity type that is opposite that of the source 106, the punch-through blocking region 118 acts as an energetic barrier with regards to carriers from the source 106 and prevents current from being leaked deeper into the fin 102 or substrate 104, thereby helping to limit punch-through.
Further, because the drain extension region 120 has the same conductivity type as the drain 108 and is electrically coupled to the drain 108, the drain extension region 120 represents a lower energetic barrier for carriers in the channel 114 and acts as a drain-extension region, which acts as a resistor to dissipate large voltages between source 106 and drain 108 such that the FinFET 100 can safely withstand higher voltages.
In one example, the integrated circuit on which the FinFET is formed includes one or more high-voltage FinFETs as shown in
A source region 212 and a drain region 214 are disposed in or adjacent to the upper fin portion 202b. The source region 212 and drain region 214 have a first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm−3 to about 1e22 cm−3). Although the lengths of the source and drain LS, LD are shown as being equal, they can also be different. The same is also true of the source and drain widths Ws, WD.
A conductive gate electrode 216 traverses over fin 202 between source region 212 and drain region 214. The conductive gate electrode 216 is typically made of metal, but could also be made out of polysilicon. A channel region 218 is defined in the semiconductor fin 202 under the conductive gate electrode 216. A gate dielectric 220 separates the conductive gate electrode 216 from the channel region 218.
A source extension region 222, which can have a smaller width WSE than that of the source 212 in some implementations, has one end 222a that is electrically coupled to the source 212 and another end 222b that can be aligned with a front edge 216a of the gate. The source extension region 222 has the first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm−3 to about 1e22 cm−3).
An intrinsic, un-doped or lightly doped semiconductor region 224 can extend continuously from the gate front edge 216a to the drain 214. This intrinsic or lightly doped semiconductor region can be made of silicon or another semiconductor material other than silicon, such as gallium arsenide for example. In one example, this region 224 can be made of silicon with the first conductivity type at a doping concentration ranging from about 1e10 cm−3 to about 1e18 cm−3. Note that although the illustrated embodiments depict one edge of the intrinsic or lightly doped semiconductor region 224 terminating under an edge of the gate electrode, the intrinsic or lightly doped semiconductor region 224 can also extend continuously between the source and drain regions.
Below the upper surface of the STI region 210, a punch-through blocking region 226 is arranged in the lower portion 202a of the semiconductor fin between the channel region 218 and the source region 212. The punch-through blocking region 226 has the first conductivity type (e.g., n-type) and can be at a doping concentration ranging from approximately 1e16 cm−3 to approximately 1e19 cm−3.
A drain extension region 228 extends between the drain region 214 and the channel region 218. The drain extension region 228 has a second conductivity type (e.g., p-type), which is opposite the first conductivity type, and can be at a doping concentration ranging from approximately 1e16 cm−3 to about 1e19 cm−3.
The punch-through blocking region 226 and drain extension region 228 often meet to form a p-n junction 230 under the gate electrode 216. For example, in
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The method starts in
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Thus, it will be appreciated that some aspects of the present disclosure relate to a fin field effect transistor (FinFET) disposed on a semiconductor substrate, comprising: a semiconductor fin disposed over the semiconductor substrate and extending between a source region and a drain region. A shallow trench isolation (STI) region that laterally surrounds a lower portion of the semiconductor fin, wherein the lower portion of the semiconductor fin lies beneath an upper surface of the STI region and an upper portion of the semiconductor fin remains above the upper surface of the STI region. A conductive gate electrode that traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A first punch-through blocking region aligned between the drain region and the channel region in the lower portion of the semiconductor fin.
Another aspect relates to a FinFET disposed on a semiconductor substrate. The FinFET comprises a semiconductor fin which is disposed over the semiconductor substrate and which extends between a source region and a drain region. The source and drain regions have a first conductive type. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the upper surface of the STI region. A conductive gate electrode traverses over the semiconductor fin to define a channel region in the upper portion of the semiconductor fin under the conductive gate electrode. A first punch-through blocking region is aligned between the source region and the channel region in the lower portion of the semiconductor fin. The first punch-through blocking region has the second conductivity type.
In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. Further, although the terms “first”, “second” “third” and the like are used in this specification, it will be appreciated that such terms are merely generic identifiers and do not imply any spatial or temporal relationship between the various features. Also, although terms such as “upper”, “lower”, “above”, and “below” are used herein, it is to be appreciated that no absolute reference frame (e.g., the ground beneath one's feet) is implied with respect to these and other similar terms. Rather, any coordinate frame can be selected for such terms. In addition, while a particular aspect may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
Claims
1. A semiconductor device disposed on a semiconductor substrate, comprising:
- a shallow trench isolation (STI) region disposed over the semiconductor substrate;
- a semiconductor fin disposed within the STI region, the semiconductor fin extending between a source region and a drain region and comprising a first portion and a second portion defined by a surface of the STI region;
- a gate electrode that traverses over the semiconductor fin to define a channel region in the semiconductor fin under the gate electrode;
- a first punch-through blocking region disposed under the source region and extending under the channel region in the second portion of the semiconductor fin; and
- a drain extension region disposed between the gate electrode and the drain region in the second portion of the semiconductor fin.
2. The device of claim 1, wherein the first punch-through blocking region and drain extension region meet at a junction region under the gate electrode.
3. The device of claim 1, further comprising:
- an intrinsic or lightly doped semiconductor region disposed in the first portion of the semiconductor fin between the source and drain regions.
4. The device of claim 3, wherein the intrinsic or lightly doped semiconductor region has a first end and a second end, wherein the first end terminates under the gate electrode and the second end connects to the drain region.
5. The device of claim 3, wherein the intrinsic or lightly doped silicon region has a first end and a second end, wherein the first end terminates under the gate electrode and the second end terminates over the drain extension region so as to be spaced apart from the drain region.
6. The device of claim 5, wherein a distance between the second end and the gate electrode is larger than a length of the channel region under the gate electrode.
7. The device of claim 3, further comprising: a gate oxide separating the gate electrode and the intrinsic or lightly doped region.
8. The device of claim 3, further comprising:
- a dummy gate formed over both the drain extension region and the intrinsic or lightly doped silicon region, the dummy gate being arranged between the gate electrode and the drain region.
9. The device of claim 8, further comprising:
- an isolation region between the dummy gate and the gate electrode, wherein the isolation region is arranged to divide the intrinsic or lightly doped region into a first part under the gate electrode and a second part under the dummy gate.
10. The device of claim 1, wherein a second punch-through blocking implant is used to form the drain extension region of the device concurrently with a second punch-through blocking region in a low-voltage transistor on the semiconductor substrate
11. The device of claim 1, wherein the source region, the drain region, and the drain extension region have a first conductivity type; and wherein the first punch-through through blocking region has a second conductivity type opposite the first conductivity type.
12. The device of claim 1, wherein the source region, the drain region, and the drain extension region are n-type; and wherein the first punch-through blocking region is p-type.
13. The device of claim 1, wherein the source region, the drain region and the drain extension region are p-type; and wherein the first punch-through blocking region is n-type.
14. The device of claim 13, further comprising: an n-type isolation region separating the drain extension region from the substrate.
15. The device of claim 1, further comprising:
- a lateral fin traversing the semiconductor fin and being coupled to a body contact.
16. The device of claim 15, further comprising a second punch-through blocking region under at least a portion of the lateral fin.
17. The device of claim 16, wherein the second punch-through blocking region has a same conductivity type as the first punch-through blocking region.
18. The device of claim 1, wherein the first region is an upper region of the semiconductor fin and the second region is a lower region of the semiconductor fin.
19. A circuit disposed on a semiconductor substrate, comprising:
- a semiconductor fin disposed over the semiconductor substrate and extending laterally between a source region and a drain region;
- a shallow trench isolation (STI) region that laterally surrounds a lower portion of the semiconductor fin, wherein an upper portion of the semiconductor fin remains above an upper surface of the STI region;
- a gate electrode that traverses over the semiconductor fin to define a channel region in the semiconductor fin under the gate electrode;
- an intrinsic or lightly doped semiconductor region in the upper portion of the semiconductor fin between the gate electrode and the drain region;
- a punch-through blocking region in the lower portion of the semiconductor fin between the source region and the channel region; and
- a drain extension region in the lower portion of the semiconductor fin between the channel region and the drain region.
20. A method of manufacturing a circuit structure comprising:
- forming a shallow trench isolation (STI) region over a semiconductor substrate;
- forming a semiconductor fin having a first portion and a second portion defined by a surface of the STI region;
- forming a drain extension region in the second portion of the semiconductor fin by using a first implant having a first conductivity type;
- forming a gate dielectric over the semiconductor fin;
- forming a gate electrode that traverses over the gate dielectric and over the semiconductor fin to define a channel region in the second portion of the semiconductor fin; and
- forming a source region and a drain region, which both have the first conductivity type, in the first portion of semiconductor fin.
21. The method of claim 20, wherein forming the drain extension region comprises concurrently forming a punch-through blocking region for a low-voltage transistor on the circuit structure.
22. The method of claim 20, further comprising:
- forming a punch-through blocking region in the second portion of the semiconductor fin with a second implant having a second conductivity type.
23. The method of claim 22, wherein forming the punch-through blocking region comprises:
- providing a first mask over an upper surface of the semiconductor fin;
- providing a second mask, which has an opening corresponding to the punch-through blocking region, over the first mask; and
- directing ions of the second implant towards the circuit structure when the first and second masks are in place to form the punch-through blocking region.
24. The method of claim 23, wherein the ions of the second implant deflect off of the STI region through sidewalls of the semiconductor fin to form the punch-through blocking region.
25. The method of claim 23, wherein forming the drain extension region comprises:
- removing the second mask;
- after the second mask has been removed, providing a third mask over the first mask, wherein the third mask comprises an opening corresponding to the drain extension region; and
- directing ions of the first implant towards the circuit structure when the first and third masks are in place to form the drain extension region.
26. The method of claim 25, wherein the third mask comprises an opening corresponding to a punch-through blocking implant region for a low-voltage transistor on the circuit structure.
27. The method of claim 25, wherein forming the drain extension region comprises deflecting the ions of the first implant off of the STI region through sidewalls of the semiconductor fin.
28. The method of claim 20, wherein forming the drain extension region comprises deflecting ions of the first implant off of the STI region through sidewalls of the semiconductor fin.
Type: Application
Filed: Jul 3, 2012
Publication Date: Jan 9, 2014
Applicant: Intel Mobile Communications GmbH (Neubiberg)
Inventors: Mayank Shrivastava (Unterhaching), Harald Gossner (Riemerling)
Application Number: 13/540,762
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);