Patents Assigned to Intermolecular
  • Patent number: 9240236
    Abstract: Provided are method for determining switching conditions for production memory cells based on dopant flux during set and reset operations. One group of test memory cells, which are representative of the production memory cells, is subjected to a prolonged application of a set voltage, while another group is subjected to a prolonged application of a reset voltage. Different durations may be used for different cells in each group. A dopant concentration profile of a test component in each cell is determined for both groups. One cell from each group may be identified such that the changes in the dopant concentration profiles in these two identified cells are complementary. The profile complementarity indicates that these two identified cells had a similar dopant flux during voltage applications. Durations of set and reset voltage applications for these two cells may be used to determine switching conditions for production memory cells.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: January 19, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik
  • Patent number: 9231203
    Abstract: Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: January 5, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Mihir Tendulkar, Milind Weling
  • Patent number: 9224799
    Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik
  • Patent number: 9221976
    Abstract: Coated article having antireflective property together with self cleaning, moisture resistance and antimicrobial properties can be prepared with a topmost layer of titanium oxide on an antireflective layer, which can be formed by a sol-gel process. The antireflective layer can comprise a porosity forming agent, or an alkyltrialkoxysilane-based binder. The antireflective coating can comprise silica and titania components, with pores to achieve low index of refraction and titania to achieve self-cleaning and antimicrobial properties.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Nikhil Kalyankar
  • Patent number: 9224639
    Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 29, 2015
    Assignees: Intermolecular, Inc., GLOBALFOUNDRIES, INC.
    Inventors: Anh Duong, Errol Todd Ryan
  • Patent number: 9224950
    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode. The ReRAM cells may also include a second layer operable as a variable resistance layer configured to switch between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have a substantially constant electrical resistivity. Moreover, the third layer may include a ternary metal-silicon nitride having a ratio of metal to silicon that is between about 1:1 and 1:4. Furthermore, the ternary metal-silicon nitride may include a metal that has an atomic weight that is greater than 90. The ReRAM cells may further include a fourth layer operable as a top electrode.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Yun Wang
  • Patent number: 9224878
    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 29, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Deweerd, Arthur Gevondyan, Hiroyuki Ode
  • Patent number: 9224594
    Abstract: Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead. Other gas distribution and gas dispersal hardware may also be used. The plasma source may be used to generate activated species operable to alter the surface of the semiconductor materials. Further, the plasma source may be used to generate activated species operable to enhance the nucleation of deposition precursors on the semiconductor surface.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Kevin Kashefi, Frank Greer
  • Patent number: 9222170
    Abstract: Anisotropic materials, such as rutile TiO2, can exhibit dielectric constant of 170 along the tetragonal axis of (001) direction, and dielectric constant of 86 along directions perpendicular to the tetragonal axis. Layer of anisotropic material nanorods, such as TiO2 nanorods, can form a seed layer to grow a dielectric layer that can exhibit the higher dielectric constant value in a direction parallel to the substrate surface. The anisotropic layer can then be patterned to expose a surface normal to the high dielectric constant direction. A conductive material can be formed in contact with the exposed surface to create an electrode/dielectric stack along the direction of high dielectric constant.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sergey Barabash, Dipankar Pramanik
  • Patent number: 9223319
    Abstract: A system and method for providing a plurality of diluted solutions are disclosed. Successive dilution operations are performed upon mixing vessels substantially simultaneously. Measured source volumes of a source solution are placed into the mixing vessels. First measured volumes of a liquid are added to the mixing vessels. Measured first waste volumes are dispensed from the mixing vessels. Second measured volumes of the liquid are added to the mixing vessels. Measured second waste volumes are dispensed from the mixing vessels. Third measured volumes of the liquid are added to the mixing vessels. Each vessel has an individual target dilution ratio. Measured volumes and number of dilution operations are individual to each of the mixing vessels.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Satbir Kahlon, Jeffrey Chih-Hou Lowe, Wen-Guang Yu
  • Patent number: 9224783
    Abstract: Defects in hydrogenated amorphous silicon are reduced by low-energy ion treatments and optional annealing. The treatments leave strongly-bonded hydrogen and other passivants in place, but increase the mobility of loosely-bonded and interstitially trapped hydrogen that would otherwise form unwanted two-level systems (TLS). The mobilized hydrogen atoms may be attracted to unused passivation sites or recombined into H2 gas and diffuse out of the deposited layer. The treatments also increase the density of the material. The optional anneal may partially crystallize the layer, further densify the layer, or both. The reduced number of defects and the increased crystallinity reduce the loss tangent of amorphous silicon dielectrics for superconducting microwave devices.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Frank Greer, Andy Steinbach, Wenxian Zhu
  • Patent number: 9224644
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 29, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Amol Joshi, Chi-I Lang, Salil Mujumdar
  • Patent number: 9224951
    Abstract: A resistive-switching memory (ReRAM cell) has a current-limiting electrode layer that combines the functions of an embedded resistor, an outer electrode, and an intermediate electrode, reducing the thickness of the ReRAM stack and simplifying the fabrication process. The materials include compound nitrides of a transition metal and one of aluminum, boron, or silicon. In experiments with tantalum silicon nitride, peak yield in the desired resistivity range corresponded to ˜24 at % silicon and ˜32 at % nitrogen, believed to optimize the trade-off between inhibiting TaSi2 formation and minimizing nitrogen diffusion. A binary metal nitride may be formed at one or more of the interfaces between the current-limiting electrode and neighboring layers such as metal-oxide switching layers.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 29, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Federico Nardi, Milind Weling
  • Patent number: 9209134
    Abstract: Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 8, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Mankoo Lee
  • Patent number: 9206078
    Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 8, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Guizhen Zhang, Jeremy Cheng, Guowen Ding, Minh Huu Le, Daniel Schweigert, Yu Wang
  • Publication number: 20150345005
    Abstract: Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. For example, by adding appropriate seed layers between the IR reflective layers and the base oxide layers, the color performance can be maintained regardless of high temperature processes. The optical filler layers can include a metal oxide layer. In some embodiments, the seed layer can include nickel, titanium, and niobium, forming a nickel titanium niobium alloy such as NiTiNb.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 3, 2015
    Applicant: Intermolecular Inc.
    Inventors: Guowen Ding, Tong Ju, Minh Huu Le, Daniel Schweigert, Guizhen Zhang
  • Patent number: 9202690
    Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. An IGZO layer is formed above the substrate. The IGZO layer is annealed in an environment consisting essentially of nitrogen gas.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 1, 2015
    Assignees: Intermolecular, Inc., LG Display Co., Ltd.
    Inventors: Sang Lee, Stuart Brinkley, Yoon-Kyung Chang, Seon-Mee Cho, Min-Cheol Kim, Kwon-Sik Park, Woosup Shin
  • Publication number: 20150338362
    Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Applicant: Intermolecular Inc.
    Inventors: Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram, Karthik Ramani, Vivian Ryan, Jingang Su, Xunyuan Zhang
  • Patent number: 9196475
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 24, 2015
    Assignees: GLOBALFOUNDRIES, INC., INTERMOLECULAR, INC.
    Inventors: Bongki Lee, Paul Besser, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon, Divya Pisharoty, Nobi Fuchigami
  • Patent number: 9184379
    Abstract: A thin cap of metal alloy or metal-silicon compound is formed over a ternary oxide or ternary nitride ReRAM embedded resistor. At least one metal in the cap is the same as a metal in the embedded resistor. If the cap oxidizes slightly (e.g., incidental to a vacuum break, anneal, or subsequent treatment or deposition), the overall resistance of the memory cell is much less affected than it would be by the same amount of oxidation directly on a surface of the uncapped oxide or nitride embedded resistor.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: November 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventor: Yun Wang