Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In2O3 showed low resistivity and low visible absorbance, both of which were thermally stable up to 400 C.

Abstract: Embodiments of the invention relate generally to methods and compositions for forming porous low refractive index coatings on substrates. In one embodiment, a method for forming a porous coating on a substrate is provided. The method comprises coating a substrate with a sol-gel composition, comprising at least one porosity forming agent, wherein the porosity forming agent is selected from at least one of dendrimers and organic nanocrystals and removing the at least one porosity forming agent to form the porous coating. Use of at least one of the dendrimers and organic nanocrystals leads to the formation of stable pores with larger volume fraction in the film. Further, the size and interconnectivity of the pores may be controlled via selection of the organic nanocrystal or dendrimer structure, the total organic nanocrystal or dendrimer molecule fraction, polarity of the organic nanocrystal or dendrimer molecule and solvent, and other physiochemical properties of the gel phase.

Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. The semiconductor substrate is exposed to bromine radicals, hydrogen radicals, or a combination thereof. An oxide layer is formed above the semiconductor substrate. The semiconductor substrate is held within a controlled atmosphere at least from the completion of the exposing of the semiconductor substrate to bromine radicals, hydrogen radicals, or a combination thereof and the beginning of the forming of the oxide layer.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped.

Abstract: Systems and apparatus are described that facilitate the evaluation and characterization of ALD processes as a function of process parameters such as temperature, gas flow rate, and pressure. In some embodiments, systems and apparatus are described that allow the ALD process to be characterized at different pressures in a combinatorial manner.

Abstract: A nonvolatile memory device and method for forming a resistive switching memory element, with improved lifetime and switching performance. A nonvolatile memory element includes resistive switching layer formed between a first and second electrode. The resistive switching layer comprises a metal oxide. One or more electrodes include a dopant material to provide the electrode with enhanced oxygen-blocking properties that maintain and control the oxygen ion content within the memory element contributing to increased device lifetime and performance.

Abstract: Provided are resistive switching memory cells having selectors and methods of fabricating such cells. A selector may be disposed between an electrode and resistive switching layer. The selector is configured to undergo an electrical breakdown when a voltage applied to the selector exceeds a selected threshold. The selector is formed from amorphous silicon doped with fluorine. The concentration of fluorine may be between about 0.01% atomic and 3% atomic, such as about 1% atomic. Amorphous silicon has a larger band gap than, for example, crystalline silicon and, therefore, has a lower leakage. Dangling bond and weak bond states appearing in the mid-gap position of amorphous silicon are eliminated by adding fluorine. Fluorine binds to and passivates defects. In some embodiments, a fluorine reservoir is positioned in a low current density region of the memory cell to counter diffusion of fluorine from the selector into other components.

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

Abstract: Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In2Se3 and In2S3.

Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract: A gas distribution structure for supplying reactant gases and purge gases to independent process cells to deposit thin films on separate regions of a substrate is described. Each process cell has an associated ring purge and exhaust manifold to prevent reactive gases from forming deposits on the surface of the wafer between the isolated regions. Each process cell has an associated showerhead for conveying the reactive gases to the substrate. The showerheads can be independently rotated to simulate the rotation parameter for the deposition process.

Abstract: Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for forming a Cu—In—Ga layer followed by partial or full selenization. This results in a higher Ga concentration at the back interface. The substrate is then exposed to an aluminum CVD precursor while the substrate is still in the selenization equipment to deposit a thin Al layer. The substrate is then exposed to a Se source to fully convert the absorber layer. This results in a higher Al concentration at the front of the absorber.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating them using metal organic chemical vapor deposition (MOCVD). Specifically, MOCVD is used to form an embedded resistor that includes two different nitrides. The first nitride may be more conductive than the second nitride. The concentrations of these nitrides may vary throughout the thickness of the embedded resistor. This variability may be achieved by changing flow rates of MOCVD precursors during formation of the embedded resistor. The second nitride may be concentrated in the middle of the embedded resistor, while the first nitride may be present at interface surfaces of the embedded resistor. As such, the first nitride protects the second nitride from exposure to other components and/or environments and prevents oxidation of the second nitride. Controlling the distribution of the two nitrides within the embedded resistor allows using new materials and achieving consistent performance of the embedded resistor.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.