Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

Abstract: An ECL circuit having an output circuit with improved pull-down characteristics. An active pull-down circuit is provided by a p-channel JFET which includes a back gate connection or a merged p-channel JFET/NPN device. The gate and/or back gate are switched, providing a lowering of the device impedance during switching of the device from pull-up to pull-down operation, resulting in an improved pull-down speed.

Abstract: A conversion system is disclosed for performing either an analog-to-digital A/D conversion associated with an amplification step or a digital-to-analog D/A conversion associated with an attenuation step. The system includes apparatus (115) for receiving a input digital word to be processed, i.e. converted into analog and then attenuated, and apparatus (165) for receiving a input analog value to be processed, i.e. amplified for scaling purposes and then converted into digital. It also includes a digital-to-analog D/A converter (110), an attenuator (120) for attenuating the analog output of D/A converter (110), and a comparator (150) for comparing the value of the input analog value to be processed and the output of said attenuator (120). The processing of the D/A-attenuation process is performed by both the D/A converter (110) and attenuator (120).

Abstract: Circuitry for implementing a gate enhanced lateral transistor to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage.

Abstract: A complementary bipolar transistor structure having one symmetrical intrinsic region for both the NPN and PNP transistors and a method for fabricating the structure. The transistor structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. In the method, the sub-emitter and the sub-collector regions are formed by depositing a first epitaxial layer of semiconductor material of a first conductivity type on the surface of a semiconductor substrate of a second conductivity type, and forming the sub-collector by etchig a shallow trench in the first layer and depositing semiconductor material of a second conductivity tyep by LTE and planarizing.

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit is connected by parallel N channel and P channel devices to serially connected N and P channel devices. The serially connected N and P channel devices are connected across a CMOS power supply with gate connections connected to the logic circuit. The parallel devices provide a regulating feedback current to one of the serially connected P channel and N channel devices during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices. The voltage at the junction of the serially connected P and N channel devices is regulated by each of the parallel connected devices.

Abstract: A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions.

Abstract: An enhanced fixed function video display terminal having various features for the efficient transmission of data streams. The video display terminal may have a memory for storing substantially more characters than can be displayed to the operator on the display screen width and length. This permits manipulation of data at document page boundaries, scrolling, etc. One or more extended attribute buffers are added to enable characters to be displayed in a variety of fonts, colors, etc. The data stream from the host computer to the display terminal and from the display terminal to the host computer contains data characters and attribute characters which are interleaved for efficiency in input/output programming. When receiving data, the display terminal has the capability of parsing the data stream into data or attribute characters and adding pad characters to completely fill the display buffers.

Abstract: A method is described for fabricating a DRAM cell in a monocrystalline substrate wherein the cell includes an FET transistor and a capacitor. The method includes the steps of providing a buried storage capacitor in a trench in the substrate; forming a semiconductor mesa area juxtaposed to the buried storage capacitor; opening a channel to a contact of the storage capacitor; depositing a semiconductor layer over the mesa area and in the opened channel; removing a substantial portion of the conductive layer while leaving at least a connecting portion of the conductive layer deposited in the channel and in communication with the semiconductor mesa; and forming an FET gate structure including a source and drain on the mesa whereby the connecting conductive portion provides a conductive path between the FET and the capacitor.

Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in-situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.

Abstract: A method of producing instructions for installing a three dimensional cable assembly in a larger assembly. A three dimensional digital computer model of the cable assembly and a larger assembly is designed ab initio by using a three dimensional mechanical design system. A three dimensional view of the model is then selected and transferred to a two dimensional representation while retaining the aspect ratios of the cable assembly. Finally, the cable assembly geometry is visually distinguished from the larger assembly so that the former assembly is clearly accentuated with respect to the latter.

Abstract: Disclosed is a multilayered metallurgical structure for an electronic component. The structure includes a base metallurgy which includes one or more layers of chromium, titanium, zirconium, hafnium, niobium, molybdenum, tantalum, cooper and/or aluminum. Directly on the base metallurgy is a layer of cobalt. The structure may also include a layer of noble or relatively noble metal such as gold, platinum, palladium and/or tin directly on the cobalt.

Abstract: A feed mechanism for transporting paper has an endless band with transport pins for insertion into the perforations in circular perforations in the paper. The feed pins are part of drive elements attached through perforations in an endless flexible band to gear teeth which are engaged by grooves in a drive pulley. The transport pins have a cap portion on top of a base portion. The cap portion is tapered in the shape of a circular involute and extends from the top of the truncated circular conical base portion. The perforations in the band have the shape of an ellipse with the major axis thereof aligned in the direction of movement of the band. The band can be either thin flexible steel or polymer and the pin portion and gear portion of the drive elements can be integral and molded from an elastomer material through the elliptical perforations in the band.

Abstract: A three terminal differentially sensitive magnetic diode structure is described. It offers high magnetic sensitivity and utilizes the Lorentz field potential modulation of injected carriers at the emitter. Two base contacts separated from the emitter are employed to derive a signal from the modulation of emitter injection in the presence of a magnetic field.

Abstract: The invention comprises an image scan apparatus wherein a simple document feed unit is provided for feeding a document to be scanned to a predetermined position on a glass platen. The document feed unit is mechanically coupled to an image sense unit which is reciprocally moved between a home position and a scan start position. The document feed unit includes a frictional roller which is in contact with the glass platen. A leading edge of the document is inserted by an operator at a home position between a frictional roller and the glass platen. The frictional roller is mounted on a shaft via a one-way clutch or one-way bearing. The one-way clutch inhibits the rotation of the frictional roller during its movement from the home position to a scan start position. The leading portion of the document is engaged by the frictional roller, and the document is fed to a predetermined position on the glass platen as the frictional roller and the image sense unit are moved to the scan start position.

Abstract: Apparatus and method for producing diamond films. A source of free electrons is used to bombard a carbon block. Incident electrons vaporize the carbon surface, and free carbon atoms are ionized from collisions of the electrons with the carbon atoms. A collimating plate located above the carbon block includes an aperture for permitting the vaporized carbon ions to be collimated. On the other side of the collimating plate are first and second deflector plates, symmetrical with respect to the axis of the collimating plate aperture. A voltage potential therebetween produces an electrostatic field perpendicular to the axis of the aperture. Substrates located in the electrostatic field receive a carbon ion film which is essentially a diamond film structure.

Abstract: Network interface software for use in a network of computers includes software providing protocols for transmission of messages without high level software acknowledgments required. Negative acknowledgments are relied on to indicate the failure of complete message reception.

Abstract: An electrical connector is described for making contact with a plurality of convex and deformable contacts on an electronic device. The electrical connector comprises a substrate having a plurality of conductors which extend above its surface. A polymeric material is disposed on the surface of the substrate and has openings which expose the conductors, each opening sized to receive one of the convex, deformable contacts, and to enable electrical connection between the exposed conductors and the deformable contacts. A mechanism is provided for urging the deformable contacts on the electronic device against the exposed conductors. The mechanism exerts sufficient force between the device and the conductors to cause some deformation of the convex contact areas by the conductors.

Abstract: An error detection apparatus is implemented in a passive device inserted on a synchronous bus, linking two devices. The bus has data lines onto which data are transferred between the two devices under control of tag lines and clock signals which are companion of the transferred data. The apparatus allows errors to be detected, the failing device to be identified and the error signals to be reported in a psuedo-synchronous way on an error bus due to error detection and reporting logic circuits and a pseudo-synchronous timing circuit.