Abstract: A write-once-read-once batteryless token stores access data using fuses similar to those found in programmable fuse link devices. These fuses indicate the status of a particular bit in either of two memory arrays. An intact fuse indicates that a bit is a logical zero, and a blown fuse indicates that a bit is a logical one. The process of reading a particular bit in either array causes the destruction of the corresponding memory cells in both arrays before the data from the selected cell becomes available to the reading device. The memory bit cells are destroyed by blowing the bit fuse during the read cycle.

Abstract: Magnetic thin film structures are disclosed including a laminate of a layer of nonmagnetic material sandwiched between first and second layers of magnetic material and at least one edge closure layer of magnetic material disposed on a side edge of the laminate with the edge closure layer being in magnetic contact with the first and second layers of magnetic material. The edge closure layer eliminates magnetic edge closure domains and magnetic edge-curling walls in the yoke and poletip regions, or in a fluxguide of a magnetic recording head to substantially eliminate Barkhausen noise and wall network instabilities. Multiple layer laminates are also disclosed having a plurality of nonmagnetic layers each of which are sandwiched between layers of magnetic material and wherein the laminate includes edge closure layers that contact all the magnetic layers. Several methods are disclosed for fabricating the laminate.

Abstract: A passive lubrication system for use in a high speed print hammer mechanism to provide continuous lubrication to all print hammers over the lifetime of the mechanism. A plurality of hammer elements are pivotally engaged by a common pivot pin element. The lubrication system comprises a hammer block and a reservoir block both made of sintered material and each containing a supply of lubricant. The hammer block supplies lubrication to the pivot pin/hammer element bearing interfaces by capillary action. The reservoir block in turn supplies lubricant to the hammer block by capillary action to replenish the supply of lubricant as depleted in the hammer block. The reservoir block has a porous microstructure in which the porosity is at least equal to but preferably in coarser than the porosity of the porous microstructure of the hammer block.

Abstract: The present invention provides a logic synthesis method and system which begins with a set of register transfer statements describing the desired logic. These statements are converted to expressions in prefix form. Next, logic reduction is performed on the individual expressions. The modified expressions are then converted to a set of logical function blocks, some of which may not be primitive blocks. Logical reduction is performed on the global set of any remaining primitives. The output of the above process is then used to synthesize the logic circuit. Included in the invention are novel techniques for performing logic reduction on the individual expressions.

Abstract: An automatic method to repair circuit shorts and near-shorts present in narrow bridges or remnants of bridges between circuit lines. By applying a voltage across a pair of lines, certain electrical phenomena take place at the area of the short or near-short. The electrical phenomena thus generated induce a localized etching in either a gas-phase or liquid-phase medium depending upon which embodiment is used.

Abstract: A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache.

Abstract: A heat exchanger for cooling an array of electric circuit chips disposed on a common substrate is formed as a flexible sheet of thermally conducting material with upstanding fins for transference of heat from the chips to a coolant flowing through the fins. Pin fins may be employed with air coolant. The sheet may be provided with corrugations set between sites of the chips for improved flexibility to accommodate individual orientations of the chips. The sheet is sufficiently large to cover an array of chips and is thermally joined, as by use of a thermally conductive grease, to the chips. The sheet hermetically seals the chips from contamination by the coolant. For liquid coolant, the heat exchanger may be fabricated of copper with a nickel coating, wherein the copper provides the heat conduction and the nickel protects the copper from a corrosive coolant such as water.

Abstract: An apparatus and method for protecting BIOS stored on a direct access storage device into a personnal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, a protection means and at least one direct access storage device. The read only memory includes a first portion of BIOS and data representing the type of system processor and system planar I/O configuration. The first portion of BIOS initializes the system and the direct access storage device, and resets the protection means in order to read in a master boot record into the random access memory from a protectable partition on the direct access storage device.

Abstract: A system for designing an intercommunication network among a plurality of devices. The system includes a device for storing rules to meet design requirements and a mechanism connected to the device for storing rules in order to revise the rules dynamically. Also provided is a device for storing data and a mechanism connected to the device for storing data in order to revise the data. A requestor has the ability to access all rules and to revise a portion of the data. Moreover, a designer has the ability to access all rules and to revise another portion of the data, which portion has at least one subportion that cannot be revised by the requestor.

Abstract: A system is described which determines the characteristics of a substantially rounded feature, such as via hole in a printed circuit board. The system includes an image scanner for providing a serial flow of a raster scan image of pixels which represent the rounded feature. Tangent detecting circuits are further provided which select groups (i.e., neighborhoods) of pixels from the scan image, each group including pixels clustered about a plurality of chosen azimuths and adjacent to a tangent to a boundary of the rounded feature. Processing circuits are further provided to trim each selected group of pixels to eliminate pixels not lying on the tangent line. The pixels which remain after the trim operation are representative of the limits (e.g., diameter, radius, etc.) of the rounded feature and enable an analyzing circuit to determine the characteristics of the rounded feature by examining the relationships between the tangent line pixels.

Abstract: An AND gate includes first and second opposite-type field effect transistors, each including first and second conduction path terminals and a control electrode. The gate's output terminal is connected, in common, to the second conduction path terminals of the transistors. A first logic input is connected to the first conduction path terminal of the first transistor and a second logic input is connected in common to the control electrode of the first transistor and to the first conduction path terminal of the second transistor. A third logic input is applied to the control electrode of the second transistor. In a standby state prior to the application of logic signals all three logic inputs are in the same state. This assures no conduction of logic signals, while conditioning the gate for rapid selection when logic signals are applied. Subsequently, logic signals are applied to the inputs with the third input being the complement level of the logic signal on the first input.

Abstract: Disclosed is a memory access control device for a memory organized in 2.sup.n byte words and having the capability of addressing each byte in a word under control of byte select signals (BS), through an m-byte wide bus 22, with 2.sup.n /m being an integer k, to write or read data byte bursts comprising a variable count of bytes. For writing, k sets of m bytes received from bus 22 are stored into 2.sup.n registers 40 during each bus period T; they are then transferred into buffer 30 which comprises successive location of 2.sup.n bytes positions, through an alignment and control logic 42, which causes the buffer to be written in such a way that it maps the data arrangement in memory. This depends upon the least significant bits of the memory starting address determining the byte location within the memory words. Once the complete data burst is written into the buffer, the buffer content is transferred to the memory.

Abstract: A thermoelectrically cooled integrated circuit package is provided which includes a thermally conductive dielectric substrate, an input connecting portion and an output connecting portion supported by the dielectric substrate, and an integrated circuit chip including an input terminal and output terminal. The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material. The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.

Abstract: A lapping machine control system which utilizes a electromechanical probe to generate a signal responsive to the separation of the laps, which also represents the thickness of the part being lapped. The separation signal, which is unsuitable for direct control since it is too noisy, is used with a best fit algorithm to estimate the time to reduce the part to the desired thickness, based on the rate of material removal provided by extrapolated line representing the best fit of the lap separation signal. The machining is terminated when the extrapolated line reaches the intercept of time and thickness.

Abstract: A neural network utilizing the threshold characteristics of a semiconductor device as the various memory elements of the network. Each memory element comprises a complementary pair of MOSFETs in which the threshold voltage is adjusted as a function of the input voltage to the element. The network is able to learn by example using a local learning algorithm. The network includes a series of output amplifiers in which the output is provided by the sum of the outputs of a series of learning elements coupled to the amplifier. The output of each learning element is the difference between the input signal to each learning element and an individual learning threshold at each input. The learning is accomplished by charge trapping in the insulator of each individual input MOSFET pair. The thresholds of each transistor automatically adjust to both the input and output voltages to learn the desired state.

Abstract: Method for determining the baud rate of a data stream by comparison of captured data to known autobaud characters. Samples are received from the communication device and stored in memory until a set of the samples are accumulated. Then, a sample clock is divided in half and the odd numbered samples are compared to a set of known autobaud characters. If a match occurs, then the sample clock is assumed to be correctly synchronized with the incoming serial data stream. If a match does not occur, then the even samples are recirculated and eight more samples are collected. The sample clock is again divided in half and the odd numbered samples are compared to the set of known autobaud characters. If a match occurs, then the sample clock is assumed to be correctly synchronized with the incoming data stream. These steps are repeated until an autobaud character match is found or an error situation is determined.

Abstract: An impact printing device for printing bar code patterns on an information carrier, the patterns including a combination of parallel thin and wide bars separated by spaces wherein the wide bars can have an imprint width which is a multiple of the thin bars, comprising a movable type carrier, a plurality of bar code type elements on said type carrier, the bar code type elements including first type elements having a pair of imprint forming parallel thin bars and second type elements having a single imprint forming thick bar, and a plurality of print hammers each defining a print position of a print line and each operable selectively to successively impact combinations of the first and second type elements at the same print position to form completed bar code imprints at the print position having a wide bar imprint with a width greater than the single thick bars of the second type elements.

Abstract: Within a data processing system, a control mechanism for supporting a data space without common segments in addition to traditional address spaces containing common segments. Logic for eliminating duplication of lookaside table entries for virtual addresses within shared segments, but not for identical virtual addresses within data address spaces is provided, as well as for overriding low address protection for store operations into data spaces. Thus, the entire virtual addressing range is available to programs wishing to use such data spaces for data isolation and data sharing.

Abstract: In an electrical circuit including a first array and a second array of electrical components mounted on a circuit board having an electrically conductive cladding, there is provided a system for interconnecting the components of the first array to the components of the second array with parallel signal channels for reduction of crosstalk among the channels. In each of the channels, there is one electrically conductive strip formed within the cladding and providing for a path of current in a first direction, and a second conductive path for current in the reverse direction. The second path includes a wire lead formed as a partial loop extending in a plane perpendicular to a plane of the cladding, and also includes a pad formed of material of the cladding and coplanar with the conductive strip. The pad is connected to a terminus of the wire loop.

Abstract: An apparatus for electromagnetically shielding electronic equipment has a first and second spaced apart housing members having a gap between them. A rigid member having a plurality of openings is interposed between them. A spring member connected to the rigid member has a plurality of spring fingers extending through openings in the rigid member. A cover member has a cam which forces the first housing member against one side of the spring member to extend the spring finger into the second housing member in order to cause an electrical connection between the first and second housing members.