Patents Assigned to International Computers Limited
  • Patent number: 5748739
    Abstract: A data processing system has a security infrastructure, including a first cryptographic support facility, a security service for user data, including a further cryptographic support facility, and a number of cryptographic algorithms, usable by said cryptographic support facilities. In order to protect against a user replacing weak algorithms intended for the protection of data with strong algorithms intended for use by the security infrastructure, a challenge/response mechanism is provided, which enables the cryptographic support facilities to verify authenticity of the algorithms. The challenge/response mechanism is as follows. First, the cryptographic support facility sends a challenge to the algorithm. The algorithm then generates a response by applying a cryptographic function to the challenge, and returns the response to the cryptographic support facility. The cryptographic support facility then checks whether the response has an expected value.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: May 5, 1998
    Assignee: International Computers Limited
    Inventor: James Press
  • Patent number: 5745399
    Abstract: An apparatus for adding two BCD numbers, avoids the need for special adders with detection of carries between BCD digits. First, a sum without carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, without any carries between BCD digits. Next, a sum with carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, with carries between BCD digits. A mask pattern is then generated, comprising a six in each BCD digit where the sum without carries is unequal to the sum with carries. A result is then generated by forming the binary sum of the two numbers and the mask pattern, with carries between BCD digits.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: April 28, 1998
    Assignee: International Computers Limited
    Inventors: John Richard Eaton, Kevin Hughes
  • Patent number: 5745572
    Abstract: A data processing system includes a number of applications, each of which has a cryptographic support facility (CSF) for securely managing cryptographic keys and performing cryptographic operations on behalf of the application. Each key has a 2-byte tag which is enciphered along with the key whenever the key is made available outside the CSF, to prevent unauthorized modification of the tag. Each tag indicates whether the key may be used as a basis for deriving data protection keys, whether keys derived from this key should be subject to cryptographic control policies, and whether the key should be subject to cryptographic control policies prior to use. Whenever the CSF is invoked to use a key, it enforces any restrictions imposed by the associated tag.
    Type: Grant
    Filed: January 17, 1996
    Date of Patent: April 28, 1998
    Assignee: International Computers Limited
    Inventor: James Press
  • Patent number: 5737741
    Abstract: A RAID system includes an array of disk units, with data mapped on to the disks as a series of stripes, each containing data and parity chunks. The data chunks of each stripe are located on radially more outer parts of the disks and the parity chunks of each stripe are located on radially more inner parts of the disks. As a result, the amount of head movement for read operations is reduced, which improves the read performance. Successive chunks within each stripe are physically located at successively more radially inward positions on successive disks, so that each stripe has a helical configuration. Mirroring can be considered as a special case in which the number of data chunks is equal to the number of parity chunks, and the parity consists of a simple replication of the data. In this case, data is written to the outermost half of a first disk and to the innermost half of a second disk, and is read from the first disk.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: April 7, 1998
    Assignee: International Computers Limited
    Inventors: Albert Stephen Hilditch, Ian Gregory Colloff
  • Patent number: 5737752
    Abstract: An n-way set-associative cache (where n is an integer greater than 1), includes a replacement mechanism for selecting a cache line for replacement. Each cache line has an associated priority tag indicating a user-defined priority for that cache line The replacement mechanism comprises an apparatus for selecting a cache line with the lowest user-defined priority in a current set of cache lines, and apparatus (e.g. based on recency of usage) for choosing between cache lines of equal priority if there is more than one cache line with said lowest user-defined priority in the current set.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: April 7, 1998
    Assignee: International Computers Limited
    Inventor: Albert Stephen Hilditch
  • Patent number: 5737763
    Abstract: Each node of a distributed (multi-node) data processing system, which includes a plurality of shared data storage disks, has a respective incremental backup bit-file containing one bit for each datablock of the shared disks. The bits are initially set to logical 0. When a node writes data to a datablock the respective bit is reset to logical 1. Upon an incremental backup requirement, one node reads all of the bit-files, forms the logical OR thereof and forms a respective new bit-file. The blocks whose bits equal 1 in this new bit-file are then backed up. The bit-files are stored in the node main memories for quick access and will be lost upon node failure. However if a redo log is maintained, bit-files can be reconstructed.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: April 7, 1998
    Assignee: International Computers Limited
    Inventor: Albert Stephen Hilditch
  • Patent number: 5721894
    Abstract: A pipelined data processing system has a jump prediction mechanism for predicting the outcomes of jump instructions. The prediction mechanism includes a jump prediction memory which provides the predictions. The jump prediction memory is addressed by a jump signature, formed by adjustably selecting bits from an address value and from a jump path value. The address value is based on the address of the jump instruction and the jump path value is based on a history of recently executed jump instructions prior to said jump instruction. A mode register is used to indicate, for each bit of the jump signature, whether that bit is to be selected from the address value or from the jump path value. Adjustment of the contents of the mode register allows fine tuning of the jump prediction mechanism to optimize performance.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: February 24, 1998
    Assignee: International Computers Limited
    Inventor: Edward William Doubtfire
  • Patent number: 5696921
    Abstract: A rotating memory system (e.g. a disk memory) in which a write request is allocated a physical block preferentially on the cylinder on which read/write heads are currently located. This reduces the amount of head movement and hence speeds up the access time. A block map is maintained to convert between the logical block numbers used by read and write requests and the physical block numbers which identify the physical locations of the blocks in the memory.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: December 9, 1997
    Assignee: International Computers Limited
    Inventor: Nicholas Peter Holt
  • Patent number: 5668991
    Abstract: A database system is described in which changes to a database file are recorded in a journal file. The journal file comprises a sequence of after-image records each having a database identifier indicating which database record it relates. Periodically, a dump is taken of the database. At regular intervals, between dumps the journal file is merged with any previously archived journal file to form a merged file, the records are sorted into order of their database identifiers and the merged file is filtered to remove all but the latest after-image record relating to each particular database record. The filtered journal file is archived. If the database file is corrupted, it can be recovered by applying the filtered journal file to a dump file. Because the journal file has been filtered, recovery is faster. The filtered journal can also be used for performing an off-line integrity check on the reconstructed database file.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: September 16, 1997
    Assignee: International Computers Limited
    Inventors: Stephen Dunn, Peter Kelbie
  • Patent number: 5659744
    Abstract: A file store for use as a work-in-progress store. Each block in the store is designated as a free block, a data block, or a forget block. When it is required to write data to the file store, a data area is created, by assigning free blocks. When it is required to discard a data area, a forget block is written into the filestore, pointing to the data area, and all the data blocks in that area are freed and added to a free chain. If at least one of the blocks in the data area pointed to by a forget block is reused, the forget block is freed and added to the free chain. The file store has advantages of a serial file organization while avoiding the garbage collection problems associated with conventional serial files.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: August 19, 1997
    Assignee: International Computers Limited
    Inventor: Richard Herbert
  • Patent number: 5644746
    Abstract: A data processing apparatus, having a visible register map for associating physical registers with logical registers. Instructions involving register-to-register transfers are executed by altering the association between the physical registers and the logical registers, without actually transferring data between the registers, so as to avoid logically redundant operations and to take such instructions out of the critical path of execution.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: July 1, 1997
    Assignee: International Computers Limited
    Inventors: Nicholas Peter Holt, John Richard Eaton
  • Patent number: 5625813
    Abstract: A database system comprises a database storing a number of records of different types. The system handles database queries, involving joins between a number of different record types. Each query is first preprocessed to identify optimal starting points for accessing the records. The system then generates a data structure comprising a number of nodes, each node representing one of the record types in the query and indicating an access method for that record type. The nodes are organized into a number of chains, each having a head node representing one of the optimal starting points, and each successive node in each chain representing a record type that can be accessed from the record type represented by a preceding node in the chain by an index mechanism, a hashed access mechanism or an ownership mechanism. A virtual row of the join is constructed by accessing each of the nodes and reading a corresponding record using the specified access method.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: April 29, 1997
    Assignee: International Computers Limited
    Inventor: John L. Venn
  • Patent number: 5615330
    Abstract: A method is described for rapidly recovering a multi-processor data processing system from failure of a boot disk. Each data processing unit in the system has a private boot disk, and at least one shared disk. The processing units are interconnected so that each processing unit has access to its own private boot disk and also to the shared disks in all of the processing units. If the boot disk of one of the processing units fails, the system is temporarily reconfigured to connect a new boot disk in place of the shared disk in that processing unit. Another of the processing units is then operated to copy the contents of its own boot disk to the new boot disk.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: March 25, 1997
    Assignee: International Computers Limited
    Inventor: Richard N. Taylor
  • Patent number: 5609746
    Abstract: In the manufacture of a printed circuit board a sacrificial tin-lead layer is deposited on the surface of the board by electroplating. Holes are then formed in the board by UV laser ablation. Debris from the ablation process is adsorbed on the sacrificial layer. The sacrificial layer is then removed by means of a chemical stripping process, along with the debris.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: March 11, 1997
    Assignee: International Computers Limited
    Inventors: Simon Farrar, Neil Taylor
  • Patent number: 5604896
    Abstract: A computer system comprises first and second processing environments interconnected by a gateway. The gateway emulates a terminal in the second environment, converting service requests from a client in the first environment into dialogues on the emulated terminal by executing scripts in a scripting language. This allows client applications in the first environment to communicate with server applications in the second environment in a way that is completely transparent to the clients. The client is not aware that it is communicating with the server through a dialogue on an emulated terminal; all knowledge of the dialogue is embodied in the scripts. This is of utility in integrating legacy computer sytems with new systems.
    Type: Grant
    Filed: April 5, 1996
    Date of Patent: February 18, 1997
    Assignee: International Computers Limited
    Inventors: Paul Duxbury, Robert C.-W. Yau
  • Patent number: 5588121
    Abstract: A parallel computer system comprises a number of processing elements, at least one communication element, an internal network interconnecting the communications and processing elements, at least one external network connected to the communications element, and a number of services resident in the elements. Each of the elements includes a protocol stack comprising transport, network, logical link and MAC (media access control) layers. Routing messages between services and the external network is performed in the MAC layer, rather than by a relay service at application level as in conventional systems. This improves the efficiency of the system, by obviating the need to pass messages up the stack to the routing function and then to pass them back down the stack again.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: December 24, 1996
    Assignee: International Computers Limited
    Inventors: Timothy G. Reddin, David S. Walsh, Jeremy S. Round
  • Patent number: 5572685
    Abstract: A computer system has a backplane including a SCSI (small computer system interface) bus for connecting a host processor to a number of disk drive units. The bus operates in a conventional manner to set up a connection, until the stage where the initiator selects a target. Then backplane control logic intervenes, and isolates all units on the bus other than the initiator and the target. Isolation is achieved by means of a set of bus switches on the backplane, controlled by the backplane control logic. This ensures that data transfer takes place over a simple one-to-one connection, reducing bus capacitance and reflections. The backplane also includes power switches that can be operated to power down any disk unit while it is being hot-swapped, and LEDs to indicate when it is safe to hot-swap a disk unit.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: November 5, 1996
    Assignee: International Computers Limited
    Inventors: John G. Fisher, Stephen Gold, Philip Worsdale
  • Patent number: 5548760
    Abstract: A computer system has a message handler for passing messages between processes. The message handler makes use of a message queue and a process queue. The message queue holds a list of messages between the processes, arranged in chronological order according to the length of time each message has been waiting for delivery. The process queue holds a list of processes that have requested messages, arranged in chronological order according to the length of time each process has been waiting for a message. The message handler searches the queues to find the earliest process in the process queue that currently has a message queued for it, and to find the earliest message in the message queue currently queued for that process, and then passes that message to that process. The message handler may be implemented as a TSR (Terminate and Stay Resident) process, running under a single-thread operating system.
    Type: Grant
    Filed: August 10, 1995
    Date of Patent: August 20, 1996
    Assignee: International Computers Limited
    Inventor: Roger K. Healey
  • Patent number: 5535411
    Abstract: A high-availability computer system comprises at least two processors, each having its own private disk drive, and a shared disk drive, accessible by both processors. Each of the private disk drives holds system files for establishing a processor as a secondary processor, and the shared disk drive holds system files for establishing a processor as a primary processor. When it boots up, each processor decides whether to use the system files from its private disk so as to become a secondary, or to use the system files from the shared disk so as to become the primary. As as result, after a system failure or reboot, either processor can pick up the characteristics of the the primary processor, and will have all the most up-to-date primary information available to it.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: July 9, 1996
    Assignee: International Computers Limited
    Inventors: Paul F. Speed, Richard N. Taylor
  • Patent number: 5530816
    Abstract: A data processing system has a scheduling unit for scheduling instructions from a number of instruction streams, and assigning those instructions to a number of execution units. A termination unit receives the results of the execution and informs the scheduling unit of which operands are available. The scheduling unit uses the operand availability information to control the scheduling of the instructions.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: June 25, 1996
    Assignee: International Computers Limited
    Inventor: Nicholas P. Holt