Abstract: A pipelined data processing system comprises a series of pipeline stages through which instructions pass sequentially. If an error associated with a particular instruction (e.g. an illegal instruction) is detected, a Mayday signal is produced. This does not become active immediately. Instead it is passed down the pipeline along with the instruction that caused it, and becomes active only if that instruction attempts to terminate at the end of the pipeline. When the Mayday becomes active, it causes an interrupt to a diagnostic processor. If, on the other hand, the instruction that caused the Mayday is aborted, or does not attempt to terminate, then the Mayday is discarded and does not become active. This prevents unnecessary diagnostic actions.

Abstract: A multi-processor data processing system, comprises a plurality of data processing modules. A set of interrupt lines are connected in parallel to all the processing modules. Each processing module has a priority level, and the lowest priority module is selected to act as an interrupt handler, with responsibility for handling all balanced interrupts. Whenever a processing module changes it priority, it clocks to see whether the interrupt handler is still the lowest priority module and, if not, causes the role of interrupt handler to be transferred.

Abstract: A data processing system is described including a host computer connected to peripherals by a Small Computer System Interface (SCSI) bus. A search processor is also attached to the SCSI bus and receives commands from the host as if it were a standard disc controller unit. The search processor responds to a write command to set up a search criterion, and then responds to a read command to perform a search, so as to retrieve data items satisfying the search criterion. If the logical unit number (LUN) in the command does not match the LUN assigned to the search processor, the command is passed transparently to the data store, allowing the host to access the data store directly.

Abstract: In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

Abstract: A data processing system comprises a number of processing nodes, each having a processor and a local store. The workload of the system is represented by packets, including function packets specifying a function and pointers to one or more argument packets to which the function is to be applied.The argument packets include stateholder packets, which represent variable values, such as semaphores real time clocks and so on. When a node processes a function packet, it checks whether any of its arguments is a stateholder resident in a different processing node. If so, the function packet is exported to the node in which the stateholder resides. This avoids the need for making copies of stateholder packets, and hence avoids any problems of copy consistency. Each function packet is allowed no more than one stateholder as a strict argument.

Abstract: An 8B:10B serial data transmission code is described, which provides an overall balance between ones and zeros, a code run bound of 4, and a worst case transition density of 40%. In addition, the code provides two special control characters which are unique in the coded bit stream and can be used for synchronization. The data can be encoded using a 256.times.8 ROM, and decoded using a 1024.times.6 ROM, with two bits being transmitted unencoded.

Abstract: A data processing system is described in which the workload is divided into packets. A plurality of processors access the packets and process them by rewriting them according to predetermined rules. Packets can be of a number of different types, including XAPP and PAPP. An XAPP packet contains a function and one or more arguments in evaluated form, so that the function can be immediately applied to the arguements. A PAPP packet is similar except that its arguments may not be in evaluated form. Processing of an active PAPP packet consists of activating other packets which evaluate the arguments of the PAPP packet, and converting the PAPP to a suspended XAPP packet, awaiting return information from those other packets. The use of different packet types allows greater efficiency, by eliminating redundant actions in processing of the packets.

Abstract: A security mechanism is described for a distributed data processing system. Each server in the system maintains a set of security ratings giving its view of the security levels within the system. When a first server wishes to initiate a connection with a second server, the two servers exchange security information, by means of messages, so as to establish an overall security level for the connection, based on a combination of the security information maintained by both servers. However, if the first server decides that the second server cannot be trusted to discuss security, messages are exchanged containing no security information, and each server establishes its own security level for the connection, based on its own locally held security information.

Abstract: A multi-cache data storage system has a number of cache units and a main memory. The caches are addressed by a virtual address. When data is updated in one of the caches, the virtual address is translated into a physical address and sent to the main memory over a bus, along with the updated data value. Each cache continuously monitors the bus for updates from other caches and checks whether it holds a data item corresponding to the physical address. If so, the data item is updated or invalidated, so as to ensure cache coherency.

Abstract: Data display apparatus is described in which data from a video RAM is displayed on a CRT monitor. The apparatus includes master and slave CRT controllers which are locked together in synchronism. In operation, the displayed is divided into a main application area and a noticeboard area. The master controller is selected for display of the main application area, and the slave controller is selected for display or the noticeboard area. This allows the two areas to be displayed with different parameters, e.g. number or characters per line, without the necessity for re-programming the CRT controllers part way through the frame.

Abstract: An image rotation circuit comprises a first-in-first-out memory (FIFO) for holding a block of data representing a portion of an image. Data is read out of the FIFO a word at a time, and written back into the FIFO with a displacement of one bit position. Thus, the data effectively travels around a spiral data path, producing a serial output stream. A shift register assembles the output data into words, representing the rotated image.

Abstract: A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.

Abstract: Multi-node data processing apparatus is described, in which the nodes are interconnected by multiple transmission links. Before a node can transmit a message, it must acquire a unique transmission sequence number (TSN) which it appends to the message when transmitted. Each node receives messages from all the links, and organizes them into strict TSN order before processing. This ensures that all the nodes process all the messages in the same sequence. The TSN may be acquired, for example, from a special ring interconnecting all the nodes.

Abstract: Video display apparatus is described in which video data is held in a dynamic random-access memory (DRAM). In each cycle, one processor access and four video accesses are made to be DRAM. The video data is de-skewed, by feeding it through two registers in series, so as to ensure that the four video data words can be sampled at equally spaced intervals, equal to one-fourth of the cycle.

Abstract: Test apparatus is described for testing a printed circuit board (PCB). The apparatus includes two test heads, one for each side of the board. Each test head carries an array of spring loaded probes for making electrical contact with the pads on the PCB. Each head also includes two optical fiber image guides for viewing alignment marks at diagonally opposite corners of the PCB, so as to indicate the degree of misalignment between the head and the PCB. The alignment can be adjusted by means of linear drive mechanisms which allow the position of the head to be adjusted in two dimensions relative to the PCB.

Abstract: Image display apparatus reads data from an image memory to produce an image on a interlaced raster-scanned display. The image can be zoomed by producing X and Y magnifications. X magnification is produced by repeating each pixel a predetermined number of times. Y magnification is produced by repeating each display line a predetermined number of times. The number of repetitions of each display line can be varied from line to line and can be different in the two frames, so as to cope with odd-number Y magnification factors. This is achieved by using a register file which holds the required line repetition counts.

Abstract: A computer network is described, consisting of a number of computers connected by a bus. Each computer in turn becomes master, and can send messages to the other computers. When it is finished its turn as master, it passes control on to the next computer by means of a relinquish message. Each computer, when it is not master, monitors the bus for messages destined for it. If it does not detect any messages within a predetermined time interval, it enters a contention mode in which it repeatedly sends a message until either (a) it receives a response to the message in which case it becomes master or (b) it receives another message, in which case it becomes a slave. Each computer sends the contention messages at a different repetition rate, chosen such that, whatever the initial phasing of the contention messages, one message from one computer will always get through within a predetermined number of transmission attempts.

Abstract: A video display unit is described in which the display is divided into segments, and the order of scanning within each segment is scrambled. A segment may consist, for example, of a row or characters. The scrambling eliminates or reduces the risk of eavesdropping on electromagnetic radiation from the video signal.

Abstract: A data transmission system is described, comprising a number of stations connected together in a ring. One of the stations acts as primary and can send a message at any time. The other stations act as secondaries and can transmit messages only when they receive a polling signal (EOP) from the primary. The primary keeps a record of the number of messages sent by each of the secondaries and, after it has itself received a predetermined number of messages, the primary attempts to pass on the role of primary to the secondary that has transmitted the greatest number of messages.

Abstract: A programmable logic array (PLA) is tested by applying a sliding-ones pattern to the bit lines from a circular shift register, and individual product lines are selected by applying a sequence of addresses from a linear feedback shift register (LFSR) to an integral decoder. Both the circular shift register and the LFSR are controlled by a common clock signal, avoiding the need for special synchronizing logic between them. The sequence lengths of the circular shift register and the LFSR are chosen to be coprime numbers. Thus, after a predetermined number of clock beats, all the crosspoints in the AND plane will have been individually tested.