Abstract: A programmable logic array (PLA) is described, having an integral decoder for selecting individual product lines. The integral decoder receives an input address by way of a set of buffers, which can be disabled so as to disable the integral decoder in normal operation. The buffers can be tested in their disabled state by means of an extra product line and extra output line. The extra product line is coupled to all the bit lines and to the extra output line, but not to any of the other output lines; the extra output line is coupled to the extra product line, but not to any of the other product lines. The buffers are tested by applying a sequence of addresses to the buffers in their disabled state, and observing the extra output line.

Abstract: A multi-node data processing system is described in which each node (10-13) includes a processor (PROC) and an inter-node switch (INS). In operation, only one INS is active. The active INS is configured to act as a star coupler, receiving messages from any of the nodes and broadcasting each message to all the nodes including the node in which that INS is located. Each non-active INS is configured to route messages from the local processor to the active INS, and to route incoming messages broadcast by the active INS to the local processor. The system can be reconfigured to make a different INS active.

Abstract: A raster scanned video display for high resolution graphics on to which a graphical cursor can be superimposed. Cursor data corresponding to the next raster line of the image is read out of a data store during the line blanking interval and stored in a fast memory. During scanning of that next raster line the cursor data is combined with the image data. By combining the cursor data with the image data in this way, on a line-by-line basis, storage space requirements in the fast memory are greatly reduced.

Abstract: A microprogram controlled data processing apparatus is described, in which each machine-level instruction is divided into a number of phases, and each phase is executed by a sequence of microinstructions. The machine-level instruction is decoded to produce a set of microprogram parameters, and in each phase of the instruction a sub-set of these parameters is selected, and broadcast over a parameter bus to individual decoders which decode the microinstructions, so as to qualify the effects of the microinstructions. The use of parameters in this way allows the same microprogram sequence to be used for several different instruction variants, and hence reduces the total size of the microprogram.

Abstract: A computer system is described, having memory cells organized in a directed graph structure by means of pointers. Each cell has a reference count, and each pointer has a weight value. If a new pointer to a cell is created by copying an existing pointer, the new and existing pointers are given weights whose sum equals the old value of the existing pointer. In this way, the sum of the weights of the pointers to any cell are maintained equal to its reference count. If a pointer is destroyed, the reference count of the cell to which it points is reduced by the weight of the pointer. Thus, when the reference count of a cell reaches zero, it is safe to assume that there are no more existing pointers to it, and hence that cell my be reclaimed (garbage-collected) for re-use.

Abstract: Search apparatus is described for locating an item which satisfies a predetermined criterion e.g. an instruction ready for execution or a free block of data. The apparatus uses a tree structure where each terminal node represents one of the items and is set if that item satisfies the criterion. A non-terminal node is set if any of its subordinate nodes is set. In order to locate an item, a path is traced through the tree, starting at the root node and passing through a series of set nodes until a set terminal node is reached.

Abstract: A decoder is described for a self-clocking code, e.g. a bi-frequency Manchester code. Transitions are detected in the encoded data and are clocked into a shift register by a clock having a frequency equal to a multiple of the data bit rate. A logic network is connected to the shift register so as to detect combinations of transitions representing encoded data bits "0" and "1". The logic network includes OR gate funnels which detect the transitions in a range of possible positions in the shift register, so as to allow for jitter in the input data signal. The circuit allows encoded data to be correctly decoded in the presence of jitter without the necessity for using a phase-locked loop.

Abstract: A data transmission system is described, comprising a plurality of processing nodes (10-13). At any given time, one of the nodes acts as a star coupler, for broadcasting messages to all the other nodes. This node uses a plurality of counters (361-363) to keep track of the amount of available space in the receive buffers (351) of the other nodes. Whenever a message is broadcast, all the counters are decremented. Conversely, whenever an acknowledgement signal is received, indicating that one of the other nodes has removed a message from its buffer, the corresponding counter is incremented. If any of the counters indicates that a buffer is full or nearly full, broadcasting is suspended. If any of the nodes develops a fault, preventing it from removing messages from its buffer, it transmits a constant stream of acknowledgement signals, thereby preventing the corresponding counter from indicating "full" and hence allowing the system to continue running.

Abstract: A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.

Abstract: A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.

Abstract: Data storage apparatus comprises a main store, for example a microprogram store, with an associated address generating circuit. In order to extend the capacity of the store, an additional store is provided, but because of physical limitations this is remote from the main store. To reduce delays in accessing data items from the additional store, a prediction circuit predicts the address of the next item to be required from the additional store and prefetches it. A control circuit checks whether the prefetched item is the correct one and, if it is not, causes a temporary hold-up in the operation of the address generation circuit to allow the correct data item to be fetched.

Abstract: A sequence generator for producing a sequence of binary numbers, comprises a counter, a priority encoder which encodes the contents of the counter, a memory addressed by the output of the encoder, an output register, and a logic circuit for modifying the contents of the output register as specified by the output from the memory. The generated sequence can readily be modified by changing the contents of the memory. The flexibility of the generator can be increased further by using as the counter a count register which is incremented by values from a further memory also addressed by the output of the encoder.

Abstract: A network provides communication between end units (1). Each end unit (1) received an entitlement to transmit in the form of a go-ahead. It is then able to transmit a frame of user data, which is broadcast by a central unit (7) to all other end units (1). When the end unit (1) transmitting the frame wishes to relinquish its entitlement to transmit it regenerats the go-ahead, which is passed by the central unit (7) to the next end unit (1) taking them in a predtermined cyclic sequence. The system allows frames to be acknowledged: the central unit (7) collects acknowledgements from end units (1) receiving the frame successfully, and when every expected station has acknowledged, returns an acknowledgement to the source end unit (1). Central units (1) may be combined to form larger systems.

Abstract: Clearance arrangement for data storage apparatus. Data items D are entered into a store 10 together with a tag T equal to the current value of a counter 11. Data items are valid only while the counter 11 retains its current value. When it is desired to clear the store 10 the counter is incremented so that items with the previous tag value are rendered invalid. On some or all of such occasions a fraction of the store locations are also cleared by setting their tags to a null value. By the time the counter has completed a cycle all locations have been cleared in this way and cannot erroneously appear to contain valid data remaining from the previous cycle. The store is out of action to allow it to be cleared only for a relatively short time. Different tag counters may be used for different data types.

Abstract: A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address field. The address field addresses a control memory so as to read out a control word. Each control word specifies the way in which the control signals are mapped on to the control bits of the microinstruction. The output of the control memory controls switching logic which connects the control bits to the specified control signal lines. This variable mapping of the control signals allows the control signals to be packed into any available space in the microinstruction, thus reducing the required number of bits in the microinstruction without any significant loss of flexibility. Certain critical control signals however are derived from fixed positions in the microinstruction so as to avoid delays. These critical control signals are confirmed by validity signals from the control memory.

Abstract: A data processing system that can execute a plurality of programs concurrently and has a display screen for displaying data associated with any one of the programs. Each program maintains display screen data indicating the current status of the program. The system maintains a REVIEW menu containing a list of the programs that have display screen data available. When a REVIEW key is pressed, the REVIEW menu is displayed. By pressing a further key, one of the listed programs can then be selected, and its display screen data is displayed on the screen. When the key is released, the information that was being displayed prior to operation of the REVIEW key is restored to the screen. A RESUME menu lists programs that are currently in a background mode, and can be called up by pressing a RESUME key, allowing one of those programs to be put into a foreground mode in which it has access to the screen.

Abstract: A digital integrated circuit comprises a number of registers each of which comprises several data bits and at least one control bit cell. In a normal operation state, all the registers act as parallel input/output registers. In a SHIFT state, the data bits and control bit cells of all the registers are linked together to from a serial shift path between a pair of external terminals allowing test data to be shifted in or out as required. In a TEST state, each register is set into one of a number of test modes, controlled by the test bit cells of that register. The test modes include a test generate mode in which the register acts as a pseudo-random number generator, and a test analyze mode in which it acts as a digital signature analyzer.

Abstract: Data processing apparatus includes a number of units connected by a bus over which each unit can send public write messages to all the other units in parallel. The units are connected in a loop by means of public write acceptance lines. Whenever a unit receives a public write message it sends an acceptance signal to the next unit in the loop. Each unit produces an error signal if it receives a public write message but does ot receive any corresponding acceptance signal, or if it receives an acceptance signal without having received a corresponding public write message. Thus, each unit checks its neighbors in the loop to ensure correct reception of the messages.

Abstract: In order to synchronize data signals transferred from a source unit to a destination unit, a clock signal is transmitted from the destination unit to the source unit and transmission of data is effected under control of the received clock signal. The received clock signal is retransmitted back to the destination unit with the trasmitted data and is used to register receipt of the data.

Abstract: A data storage apparatus uses a store having a nibble mode facility which allows two words to be accessed in a single extended cycle. Store access requests are held in a first-in-first-out queue in a buffer. When processing strings of data, double-read requests are alternated with pairs of write requests. A read request may be incorrectly aligned i.e. it may occur between a related pair of write requests. When an incorrectly aligned read request is detected, it is given priority so that it is executed ahead of its normal turn, and is then skipped when it is encountered during normal sequential read-out from the buffer. This allows the pair of write requests to be grouped together for execution in a single extended cycle.