Abstract: A power converter driver that is supplied with two different voltages.

Abstract: One disclosed embodiment is a power conversion circuit including a power conversion bridge between a bus voltage and ground, including a switched node for supplying current to an output circuit. A driver section is configured to drive the power conversion bridge that includes a first section and a second section, the first section being between a negative supply voltage and ground, and the second section being between the switched node and a derived voltage below the switched node, the derived voltage being derived from the negative voltage. In one embodiment, the power conversion bridge includes a high side III-nitride switch and a low side III-nitride switch connected with the high side III-nitride switch to from a half-bridge. In one embodiment, the high side and low side III-nitride switches are depletion mode devices.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: A ballast circuit operable to drive a high intensity discharge lamp in accordance with an embodiment of the present applications includes an energy conversion circuit operable to convert an input voltage into a bus voltage and to provide the bus voltage to a DC bus, a first half bridge connected across the DC bus and operable to control an output voltage supplied to the lamp, a control circuit operable to control the half bridge such that a desired output voltage is provided to the lamp, a series inductor connected in series between the half bridge and the lamp; and a parallel capacitor resistor connected across the lamp. The control circuit operates the half bridge at a high frequency for a set period of time such that a high voltage is built up across the parallel resistor, and then reduces the frequency of the half bridge until it approaches a resonance frequency which ignites the lamp.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: A circuit for using a high voltage gate driver IC (HVIC) for regulation of external floating voltage sources without use of regulation circuits. The circuit including high and low switches; at least one external voltage source coupled to the high and low switches; an HVIC having at least one internal charge pumping voltage source circuit, the HVIC being coupled to gate terminals of the high and low switches; and at least one charge pumping capacitor coupled to the at least one internal charge pumping voltage source circuit for regulating the external voltage of at least one external voltage source.

Abstract: According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example.

Abstract: Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT.

Abstract: A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.

Abstract: A process for forming a trench Schottky barrier device includes the forming of an oxide layer within the trenches in the surface of a silicon wafer, and then depositing a full continuous metal barrier layer over the full upper surface of the wafer including the trench interiors and the mesas between trenches with a barrier contact made to the mesas only. Palladium, titanium or any conventional barrier metal can be used.

Abstract: Gallium nitride material structures are provided, as well as devices and methods associated with such structures. The structures include a diamond region which may facilitate conduction and removal of heat generated within the gallium nitride material during device operation. The structures described herein may form the basis of a number of semiconductor devices and, in particular, transistors (e.g., FETs).

Abstract: A multi chip housing has a lead frame to which plural die are soldered. A heat spreader conductive cap encloses a volume containing the plural die or chips and is fixed to the periphery of the lead frame. The tops of the die are closely spaced from the interior of the cap and the volume is filled with a thermally conductive, electrically insulating plastic encapsulant.

Abstract: Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and lifetime.

Abstract: Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.

Abstract: In an example configuration, a power supply manager receives an output current value representing an amount of output current supplied by one or more power converter phases to a load. The power supply manager also receives a duty cycle value representing a duty cycle for controlling operation of the at least one power converter phase. The power supply manager produces an estimate of input current supplied to the power supply circuit based at least in part on multiplying the output current value by the duty cycle value. Contrary to conventional methods such as physically measuring an input current using complex measuring circuitry, embodiments herein include utilizing parameter information such as output current information and duty cycle information to deduce an amount of input current.

Abstract: A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage including high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit including a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal, wherein a large inrush current flowing into the output capacitor when the circuit is starting up is minimized.

Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: A process for the fabrication of a MOSgated device that includes a plurality of spaced trenches in the termination region thereof.