Patents Assigned to International Superconductivity Technology Center
  • Publication number: 20060166831
    Abstract: The invention relates to a technique for forming a thin film of good quality on a base substance via an intermediate layer. Such a film formation technique is suitably applicable to formation of an oxide high-temperature superconductor thin film usable for a superconducting wire material, a superconducting device or the like. In the method of forming a thin film on a base substance via an intermediate layer, an interface energy Ea at an interface A between the base substance and the intermediate layer, an interface energy Eb at an interface B between the intermediate layer and the thin film, and an interface energy Ec at an interface C between the base substance and the thin film in a state where the intermediate layer is omitted are calculated, and then a substance for the intermediate layer is selected so as to satisfy conditions of Ea<Ec and Eb<Ec.
    Type: Application
    Filed: October 29, 2003
    Publication date: July 27, 2006
    Applicants: Sumitomo Electric Industries, Ltd., International Superconductivity Technology center, the Juridical Foundation
    Inventors: Katsuya Hasegawa, Teruo Izumi, Yuh Shiohara, Yoshihiro Sugawara, Tsukasa Hirayama, Fumiyasu Oba, Yuichi Ikuhara
  • Patent number: 7081417
    Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: July 25, 2006
    Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial Foundation
    Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 7075171
    Abstract: A superconducting system that includes an interface circuit capable of making the best use of a high-speed superconducting circuit and a high-speed semiconductor circuit. A multi-chip module in which an Nb superconducting circuit having josephson junctions formed by the use of Nb and an oxide high-temperature superconducting latch interface circuit having josephson junctions formed by the use of an oxide high-temperature superconductor are connected is located in a low temperature environment kept at 4.2 K. The oxide high-temperature superconducting latch interface circuit is connected to a high-speed semiconductor amplifier and a signal outputted from the Nb superconducting circuit is transmitted to the high-speed semiconductor amplifier.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: July 11, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center
    Inventor: Tsunehiro Hato
  • Patent number: 7069065
    Abstract: There is provided is a method of manufacturing a superconductor layer, including preparing a coating solution by dissolving trifluoroacetates of at least one metal selected from the group consisting of yttrium and lanthanoids, barium, and copper in a solvent, coating a main surface of a substrate with the coating solution to form a coating film, subjecting the coating film to a calcining process in an atmosphere containing oxygen, and subjecting the coating film after the calcining process to a firing process in an atmosphere containing water vapor at a temperature higher than that at the calcining process. The calcining process is carried out such that the coating film after the calcining process and before the firing process have an average CuO particle diameter equal to or less than 25 nm.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: June 27, 2006
    Assignees: Kabushiki Kaisha Toshiba, Chubu Electric Power Co., Inc., Hitachi Cable Ltd., International Superconductivity Technology Center
    Inventors: Takeshi Araki, Toshiharu Niwa, Takemi Muroga, Yutaka Yamada, Izumi Hirabayashi
  • Patent number: 7046110
    Abstract: There is established a superconducting magnet made of a high-temperature bulk superconductor and capable of trapping a high magnetic field with ease and stably. The superconducting magnet made of the high-temperature bulk superconductor, for use by trapping a magnetic field, is made of the bulk superconductor provided with an artificial hole, a low melting metal impregnated into, and filling up at least the artificial hole, and a heat conducting metal material embedded with portions of the high-temperature bulk superconductor, impregnated with, and filled with the low melting metal. The superconducting magnet can be produced by a process comprising the steps of providing the artificial hole in the high-temperature bulk superconductor, disposing the heat conducting metal material in at least the artificial hole, applying a process of impregnating and filling up at least the artificial hole with the low melting metal, and subsequently, executing a process of magnetizing.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: May 16, 2006
    Assignees: International Superconductivity Technology Center, The Juridical Foundation, Railway Technical Research Institute, The Juridical Foundation
    Inventors: Masaru Tomita, Masato Murakami
  • Patent number: 7001870
    Abstract: The present invention provides a method for joining an RE123 oxide superconductor matrix obtained by a melt process by the use of a solder material. The (110) plane of an RE123 oxide superconductor matrix obtained by a melt process is used as the plane to be joined, a solder material composed of an RE123 oxide superconductor having a lower melting point than the above-mentioned RE123 oxide superconductor is interposed between the planes to be joined, and this solder material is melted and then solidified to form a joining layer, thereby joining the matrices. The solder material can be a sinter, a melt-processed material, a powder, a slurry, or a molded powder.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: February 21, 2006
    Assignee: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Kazumasa Iida, Junko Yoshioka, Naomichi Sakai, Masato Murakami
  • Patent number: 6999806
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 14, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6953770
    Abstract: The present invention relates to an MgB2-based superconductor that is easy to manufacture and well suited to mass production, and that exhibits excellent superconducting characteristics (such as a high critical current density) while still retaining the high critical temperature characteristics of MgB2. A powder mixture of magnesium, boron, and titanium is pressed into a pellet, and this product is sintered under an atmospheric pressure and other conditions (preferably at 600° C. or higher) to manufacture an MgB2-based superconductor in which titanium and/or a titanium compound are dispersed in polycrystalline MgB2. The composition of the MgB2-based superconductor is preferably adjusted to have an atomic ratio of Mg:B:Ti=x:2:y, 0.7<x<1.2 and 0.05<y<0.3, and more preferably 0.07<y<0.2, by adjusting the amounts in which the raw materials are added.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: October 11, 2005
    Assignee: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Yong Zhao, Yong Feng, Yuan Wu, Takato Machi, Yasunori Fudamoto, Naoki Koshizuka, Masato Murakami
  • Patent number: 6922066
    Abstract: In a sampler for use in measuring a waveform of an electric signal, a measurement target current is given as the electric signal to a sampler chip 11 and is also used to produce a trigger current Itr for determining measurement timing on the sampler chip. A comparator 20 compares a sum of a feedback current, a current derived from the measurement target current, and the trigger current Itr with a threshold value to produce an SFQ pulse when the sum exceeds the threshold value. The SFQ pulse produced by the comparator is observed or counted for a predetermined duration to measure the waveform of the electric signal.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 26, 2005
    Assignees: NEC Corporation, International Superconductivity Technology Center
    Inventor: Mutsuo Hidaka
  • Publication number: 20050078022
    Abstract: A circuit includes a latch circuit including a Josephson junction and configured to perform a latch operation based on a hysteresis characteristic in response to a single flux quantum, a load circuit including load inductance and load resistance and coupled to an output of the latch circuit, and a reset circuit provided between the output of the latch circuit and the load circuit and configured to reset the latch circuit a predetermined time after the latch operation by the latch circuit, wherein the Josephson junction is driven by a direct current.
    Type: Application
    Filed: August 27, 2004
    Publication date: April 14, 2005
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Satoru Hirano, Hideo Suzuki, Keiichi Tanabe, Akira Yoshida, Tsunehiro Hato, Michitaka Maruyama
  • Patent number: 6821930
    Abstract: An aqueous solution of mixed metal acetate including one kind or more of element selected from lanthanide series and yttrium, barium and copper is mixed with trifluoroacetic acid to prepare a solution of mixed metal trifluoroacetate. From a solution of mixed metal trifluoroacetate obtained thus, purified mixed metal trifluoroacetate of which total content of water and acetic acid is 2% by weight or less is prepared. With purified mixed metal trifluoroacetate, an oxide superconductor of excellent performance may be prepared.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: November 23, 2004
    Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Takeshi Araki, Katsuya Yamagiwa, Izumi Hirabayashi
  • Publication number: 20040192559
    Abstract: There is provided is a method of manufacturing a superconductor layer, including preparing a coating solution by dissolving trifluoroacetates of at least one metal selected from the group consisting of yttrium and lanthanoids, barium, and copper in a solvent, coating a main surface of a substrate with the coating solution to form a coating film, subjecting the coating film to a calcining process in an atmosphere containing oxygen, and subjecting the coating film after the calcining process to a firing process in an atmosphere containing water vapor at a temperature higher than that at the calcining process. The calcining process is carried out such that the coating film after the calcining process and before the firing process have an average CuO particle diameter equal to or less than 25 nm.
    Type: Application
    Filed: April 7, 2004
    Publication date: September 30, 2004
    Applicants: KABUSHIKI KAISHA TOSHIBA, CHUBU ELECTRIC POWER CO., INC., HITACHI CABLE LTD., International Superconductivity Technology Center
    Inventors: Takeshi Araki, Toshiharu Niwa, Takemi Muroga, Yutaka Yamada, Izumi Hirabayashi
  • Patent number: 6790675
    Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignees: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Yoshihiro Ishimaru, Masahiro Horibe, Osami Horibe, Yoshinobu Tarutani, Keiichi Tanabe
  • Patent number: 6787504
    Abstract: The invention is intended to establish means for manufacturing MB2 single crystals and to provide a useful superconductive material (wire rod and so forth) taking advantage of anisotropic superconductive properties thereof. A mixed raw material of Mg and B or a precursor containing MgB2 crystallites, obtained by causing reaction of the mixed raw material of Mg and B, kept in contact with hexagonal boron nitride (hBN), is held at a high temperature in the range of 1300 to 1700° C. and under a high pressure in the range of 3 to 6 GPa to cause reaction for forming an intermediate product, thereby growing the MB2 single crystals having anisotropic superconductive properties via the intermediate product.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: September 7, 2004
    Assignee: International Superconductivity Technology Center, The Juridicial Foundation
    Inventors: Lee Sergey Romonovich, Ayako Yamamoto, Setsuko Tajima
  • Patent number: 6743533
    Abstract: An oxide superconductor of the present invention characterized in that it comprises: a substrate 1 made of metals having a high melting temperature; at least one oxide intermediate layer 2 and 3 which is formed on at least one surface of the substrate 1; and a thick film oxide superconductor layer 5 which is formed on the oxide intermediate layer 2 and 3 the liquid phase epitaxial method in which the substrate 1 provided with the oxide intermediate layer 2 and 3 is put into a solution 7 containing the elements comprising an oxide superconductor layer, and is then pulled out from the solution 7.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: June 1, 2004
    Assignees: Fujikura Ltd., Tokyo Electric Power Company, Inc., Railway Technical Research Institute, Sumitomo Electric Industries, Ltd., International Superconductivity Technology Center
    Inventors: Kazuomi Kakimoto, Natsuro Hobara, Teruo Izumi, Yuh Shiohara, Yuichi Nakamura, Kazuya Ohmatsu, Koso Fujino
  • Patent number: 6740623
    Abstract: An Hg- or Nd-based oxide superconductor comprises Ba as a constituent element and has a content of carbon as an impurity at a level of not greater than 2.0 atomic % whereby the oxide superconductor stably shows high superconducting characteristics without causing degradation with time. For its production, BaO, which has a reduced content of carbon impurity of 0.5% or below, is provided as a feed stock for Ba, and the starting materials are mixed and processed in a dry atmosphere wherein an amount of a carbon-containing gas is suppressed to a certain level, thereby obtaining the oxide superconductor.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: May 25, 2004
    Assignee: International Superconductivity Technology Center
    Inventors: Ayako Yamamoto, Wei-Zhi Hu, Setsuko Tajima
  • Patent number: 6725248
    Abstract: A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: April 20, 2004
    Assignees: Hitachi, Ltd., International Superconductivity Technology Center, NEC Corporation, Kabushiki Kaisha Toshiba
    Inventors: Haruhiro Hasegawa, Kazunori Miyahara, Tatsunori Hashimoto, Shuichi Nagasawa, Youichi Enomoto
  • Patent number: 6724216
    Abstract: A rapid single-flux-quantum RSFQ logic circuit includes a first circuit portion having a first end grounded and having in-series connected first and second Josephson junctions. A second circuit portion has a first end grounded and has in-series connected third and fourth Josephson junctions. A first inductance element connects a second end of the first circuit portion to a second end of the second circuit portion. A tap is provided in the first inductance element, an input current signal being supplied to the tap. A bias current source is connected to a first connection node between the first and second Josephson junctions. A second inductance element connects the first connection node to a second connection node between the third and fourth Josephson junctions. A superconducting quantum interference device has fifth and sixth Josephson junctions and is coupled to the second inductance element through a magnetic field.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: April 20, 2004
    Assignees: Fujitsu Limited, NEC Corporation, International Superconductivity Technology Center, The Juridicial Foundation
    Inventors: Hideo Suzuki, Shuichi Nagasawa, Kazunori Miyahara, Youichi Enomoto
  • Patent number: 6719924
    Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: April 13, 2004
    Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Toshihiko Nagano, Jiro Yoshida
  • Publication number: 20040053079
    Abstract: A high temperature superconducting device includes a substrate (1), a ground plane (2) formed on the substrate with a prescribed pattern and made of an oxidic superconducting material, and a dielectric layer (3) formed on the substrate so as to surround the ground plane. The dielectric layer has the same crystal structure as the oxidic superconducting material and with a heat absorbance closer to that of the oxidic superconducting material than to that of the substrate.
    Type: Application
    Filed: August 6, 2003
    Publication date: March 18, 2004
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER
    Inventors: Masahiro Horibe, Yoshihiro Ishimaru, Osami Horibe, Keiichi Tanabe